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ORCIDValentin Muresan
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2010 – 2019
- 2016
[c14]Valentin Muresan:
Superior vision: Always on human-like vision for intelligent devices. SACI 2016: 229-230- 2011
- [c13]Valentin Stangaciu
, Georgiana Macariu, Mihai V. Micea, Valentin Muresan, Brendan Barry:
Requirements of a real-time multiprocessor operating system for multimedia applications. SACI 2011: 209-215
2000 – 2009
- 2006
- [c12]Andrew Kinane, Valentin Muresan, Noel E. O'Connor:
Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm. EvoWorkshops 2006: 296-307 - [c11]Andrew Kinane, Valentin Muresan, Noel E. O'Connor:
Towards an optimised VLSI design algorithm for the constant matrix multiplication problem. ISCAS 2006 - [c10]Daniel Larkin, Valentin Muresan, Noel E. O'Connor:
A low complexity hardware architecture for motion estimation. ISCAS 2006 - [c9]Daniel Larkin, Andrew Kinane, Valentin Muresan, Noel E. O'Connor:
An Efficient Hardware Architecture for a Neural Network Activation Function Generator. ISNN (2) 2006: 1319-1327 - 2005
- [c8]Andrew Kinane, Alan Casey, Valentin Muresan, Noel E. O'Connor:
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator. FPT 2005: 317-318 - 2004
- [j1]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints. J. Electron. Test. 20(1): 61-78 (2004) - [c7]Andrew Kinane, Valentin Muresan, Noel E. O'Connor, Noel Murphy, Seán Marlow:
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT. PATMOS 2004: 780-788 - 2001
- [c6]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Mixed Classical Scheduling Algorithms and Tree Growing Technique in Block-Test Scheduling under Power Constraints. IEEE International Workshop on Rapid System Prototyping 2001: 162-167 - 2000
- [c5]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Distribution-graph based approach and extended tree growing technique in power-constrained block-test scheduling. Asian Test Symposium 2000: 465-470 - [c4]Valentin Muresan, Xiaojun Wang, Mircea Vladutiu:
The left edge algorithm in block test scheduling under power constraints. ISCAS 2000: 351-354 - [c3]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
A comparison of classical scheduling approaches in power-constrained block-test scheduling. ITC 2000: 882-891 - [c2]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
Power-Constrained Block-Test List Scheduling. IEEE International Workshop on Rapid System Prototyping 2000: 182-187 - [c1]Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu:
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power Constraints. VTS 2000: 417-422
Coauthor Index
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