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ORCIDJonathan Saul
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2000 – 2009
- 2001
[j1]Alistair A. McEwan
, Jonathan Saul:
A High Speed Reconfigurable Firewall Based On Parameterizable FPGA-based Content Addressable Memories. J. Supercomput. 19(1): 93-103 (2001)
1990 – 1999
- 1999
- [c10]Jonathan Saul:
Hardware/Software Codesign for FPGA-based Systems. HICSS 1999 - [c9]Alistair McEwan, Jonathan Saul, Andrew Bailey:
A High Speed Reconfigurable Firewall Based on Parameterization FPGA-Based Content Addressable Memories. PDPTA 1999: 1138-1144 - 1998
- [c8]Maurice Kilavuka Inuani, Jonathan Saul:
Re-synthesis in technology mapping for heterogeneous FPGAs. ICCD 1998: 202-204 - 1997
- [c7]Maurice Kilavuka Inuani, Jonathan Saul:
Technology mapping of heterogeneous LUT-based FPGAs. FPL 1997: 223-234 - 1996
- [c6]Nigel Lester, Jonathan Saul:
Logic Synthesis for FPGAs Using A Mixed Exclusive-/Inclusive-OR Form. FPL 1996: 185-192 - 1995
- [c5]Tomasz Kozlowski, Erik L. Dagless, Jonathan Saul:
An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions. ICCD 1995: 244-249 - 1994
- [c4]Krzysztof Bilinski, Erik L. Dagless, Jonathan Saul, Janusz Szajna:
An efficient verification algorithm for parallel controllers. EURO-DAC 1994: 302-307 - [c3]Aiguo Lu, Jonathan Saul, Erik L. Dagless:
Architecture Oriented Logic Optimization for Lookup Table Based FPGAs. ICCD 1994: 26-29 - 1992
- [c2]James Pardey, Tomasz Kozlowski, Jonathan Saul, Martin Bolton:
State Assignment Algorithms for Parallel Controller Synthesis. ICCD 1992: 316-319 - 1991
- [c1]Jonathan Saul:
An Algorithm for the Multi-Level Minimazation of Reed-Muller Rpresentations. ICCD 1991: 634-637
Coauthor Index
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