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ORCIDChuan Lin 0002
Person information
- affiliation: Magma Design-Automation, Inc., San Jose, CA, USA
- affiliation (PhD): Northwestern University, Evanston, IL, USA
Other persons with the same name
- Chuan Lin — disambiguation page
- Chuan Lin 0001
![[0000-0001-6811-3851]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-6811-3851")
— Dalian University of Technology, Dalian, China - Chuan Lin 0003 — Nanjing University of Aeronautics and Astronautics, College of Automation Engineering, China (and 1 more)
- Chuan Lin 0004 — Beihang University, School of Electronic and Information Engineering, Beijing, China
- Chuan Lin 0005 — Southwest Jiaotong University, Chengdu, China
- Chuan Lin 0006 — Fuzhou University, Fuzhou, China
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2000 – 2009
- 2007
[j5]Chuan Lin, Hai Zhou:
Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1222-1232 (2007)- [c10]Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee:
Retiming for Synchronous Data Flow Graphs. ASP-DAC 2007: 480-485 - [c9]Chuan Lin, Hai Zhou:
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains. ASP-DAC 2007: 541-546 - [c8]Chuan Lin, Aiguo Xie, Hai Zhou:
Design closure driven delay relaxation based on convex cost network flow. DATE 2007: 63-68 - 2006
- [j4]Chuan Lin, Hai Zhou:
Optimal wire retiming without binary search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1577-1588 (2006) - [j3]Chuan Lin, Jia Wang, Hai Zhou:
Clustering for Processing Rate Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1264-1275 (2006) - [c7]Chuan Lin, Hai Zhou:
An efficient retiming algorithm under setup and hold constraints. DAC 2006: 945-950 - [c6]Chuan Lin, Hai Zhou, Chris C. N. Chu:
A revisit to floorplan optimization by Lagrangian relaxation. ICCAD 2006: 164-171 - 2005
- [j2]Chuan Lin, Hai Zhou:
Wire retiming as fixpoint computation. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1340-1348 (2005) - [c5]Chuan Lin, Jia Wang, Hai Zhou:
Clustering for processing rate optimization. ICCAD 2005: 189-195 - [c4]Chuan Lin, Hai Zhou:
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk. ICCAD 2005: 329-334 - 2004
- [j1]Hai Zhou, Chuan Lin:
Retiming for wire pipelining in system-on-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1338-1345 (2004) - [c3]Chuan Lin, Hai Zhou:
Wire Retiming for System-on-Chip by Fixpoint Computation. DATE 2004: 1092-1097 - [c2]Chuan Lin, Hai Zhou:
Optimal wire retiming without binary search. ICCAD 2004: 452-458 - 2003
- [c1]Chuan Lin, Hai Zhou:
Retiming for Wire Pipelining in System-On-Chip. ICCAD 2003: 215-220
Coauthor Index
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