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ORCIDRamyanshu Datta
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2010 – 2019
- 2010
[j3]Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka
, Jacob A. Abraham:
On-Chip Delay Measurement Based Response Analysis for Timing Characterization. J. Electron. Test. 26(6): 599-619 (2010)- [c10]Ramyanshu Datta, Mahit Warhadpande, Dale Heaton, S. Aarthi, Ram Jonnavithula:
Case studies of mixed-signal DFT. ISQED 2010: 582-589
2000 – 2009
- 2009
- [c9]Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta:
A novel architecture for on-chip path delay measurement. ITC 2009: 1-10 - 2008
- [j2]Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Performance-Optimized Design for Parametric Reliability. J. Electron. Test. 24(1-3): 129-141 (2008) - [j1]Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization. J. Electron. Test. 24(5): 481-496 (2008) - [c8]Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta:
Path-RO: a novel on-chip critical path delay measurement under process variations. ICCAD 2008: 640-646 - 2006
- [c7]Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka:
Adaptive Design for Performance-Optimized Robustness. DFT 2006: 3-11 - [c6]Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham:
A Scheme for On-Chip Timing Characterization. VTS 2006: 24-29 - 2005
- [c5]Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham:
Testing and debugging delay faults in dynamic circuits. ITC 2005: 10 - 2004
- [c4]Ramyanshu Datta, Antony Sebastine, Jacob A. Abraham:
Delay fault testing and silicon debug using scan chains. ETS 2004: 46-51 - [c3]Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham:
On-chip delay measurement for silicon debug. ACM Great Lakes Symposium on VLSI 2004: 145-148 - [c2]Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480 - [c1]Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu:
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ITC 2004: 1118-1127
Coauthor Index
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