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ORCIDSherif M. Sharroush
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Journal Articles
- 2024
[j10]Sherif M. Sharroush, Yasser S. Abdalla
:
Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element. Integr. 96: 102154 (2024)- 2023
- [j9]Sherif M. Sharroush, Emad Badry:
Proposed time-mode wide fan-in NAND and NOR gates. Int. J. Circuit Theory Appl. 51(7): 3480-3513 (2023) - 2020
- [j8]Sherif M. Sharroush:
Inverter-based voltage-controlled and programmable comparators. Int. J. Circuit Theory Appl. 48(7): 1070-1092 (2020) - 2019
- [j7]Sherif M. Sharroush:
Design of the CMOS inverter-based amplifier: A quantitative approach. Int. J. Circuit Theory Appl. 47(7): 1006-1036 (2019) - [j6]Sherif M. Sharroush:
A predischarged bitline 1T-1C DRAM readout scheme. Microelectron. J. 83: 168-184 (2019) - 2018
- [j5]Sherif M. Sharroush:
Time-Domain Readout of 1T-1C DRAM Cells. J. Circuits Syst. Comput. 27(1): 1850005:1-1850005:36 (2018) - 2017
- [j4]Sherif M. Sharroush:
A voltage-controlled ring oscillator based on an FGMOS transistor. Microelectron. J. 66: 167-186 (2017) - 2016
- [j3]Sherif M. Sharroush:
Performance optimization of 1T-1C DRAMs: A quantitative study. Microelectron. J. 52: 147-164 (2016) - 2014
- [j2]Sherif M. Sharroush:
Reading DRAM cells using two properly designed cascaded inverters. Elektrotech. Informationstechnik 131(2): 41-52 (2014) - 2012
- [j1]Sherif M. Sharroush, Yasser S. Abdalla, Ahmed A. Dessouki, El-Sayed A. El-Badawy:
Dynamic random-access memories without sense amplifiers. Elektrotech. Informationstechnik 129(2): 88-101 (2012)
Conference and Workshop Papers
- 2020
- [c7]Sherif M. Sharroush:
Optimum Sizing of the Sleep Transistor in MTCMOS Technology. NILES 2020: 1-6 - [c6]Sherif M. Sharroush:
An MTCMOS Subthreshold-Leakage Reduction Algorithm. NILES 2020: 7-14 - 2019
- [c5]Sherif M. Sharroush:
A Novel Current-Domain DRAM Readout Scheme. ICM 2019: 249-252 - 2015
- [c4]Sherif M. Sharroush:
A novel self-referenced ferroelectric-memory readout scheme. ICECS 2015: 105-108 - [c3]Sherif M. Sharroush:
An alternative to CMOS stacks based on a floating-gate transistor. ICECS 2015: 109-112 - 2013
- [c2]Sherif M. Sharroush:
Low-power and high-speed DRAM readout scheme. ICECS 2013: 791-794 - 2007
- [c1]Aly E. Salama, Sherif M. Sharroush, Mahmoud Y. Fekry:
Increasing the Sense Margin of 1T-1C Ferroelectric Random-Access Memories. ISCAS 2007: 2268-2271
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