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ORCIDIan P. Jalowiecki
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Journal Articles
- 1991
[j2]R. Mike Lea, Ian P. Jalowiecki:
Associative massively parallel computers. Proc. IEEE 79(4): 469-479 (1991)- 1988
- [j1]Simon R. Jones, Ian P. Jalowiecki, Stephen J. Hedge, R. Mike Lea:
A 9-kbit associative memory for high-speed parallel processing applications. IEEE J. Solid State Circuits 23(2): 543-548 (1988)
Conference and Workshop Papers
- 2001
- [c7]Argy Krikelis, Ian P. Jalowiecki, David L. Bean, Ryan Bishop, M. Facey, D. Boughton, S. Murphy, M. Whitaker:
A programmable processor with 4096 processing units for media applications. ICASSP 2001: 937-940 - 1996
- [c6]Chryssa Dislis, Ian P. Jalowiecki:
Economics Modelling and Optimisation of MCM Test Strategies. ED&TC 1996: 615 - [c5]Thomas Gneiting, Ian P. Jalowiecki:
The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes. DFT 1996: 140-148 - 1995
- [c4]Chryssa Dislis, A. F. Al-Ani, Ian P. Jalowiecki:
MCM Quality and Cost Analysis Using Economics Models. ITC 1995: 430-437 - 1994
- [c3]Darren Patrick Rodohan, Ray J. Glover, Ian P. Jalowiecki:
An Implementation Of A Set Mode For Prolog On A Parallell Associative Processor. PDP 1994: 413-419 - 1993
- [c2]Claus M. Habiger, Ian P. Jalowiecki:
The implementation of a MCM associative string processor. VLSI 1993: 283-289 - 1991
- [c1]Ian P. Jalowiecki, Stephen J. Hedge:
The WASP 2 Wafer Scale Integration Demonstrator. VLSI 1991: 491-500
Coauthor Index
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