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ORCIDBaljit Kaur
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2020 – today
- 2024
[j8]Vadthya Bheemudu, Vaithiyanathan Dhandapani, Baljit Kaur:
Design insights into a junctionless nanosheet FET (JL-NSFET) for switching and Analog/RF applications: Device to circuit level assessment. Microelectron. J. 149: 106220 (2024)- 2023
- [j7]Alok Kumar Mishra
, Shail Anand, Nishant Singh, Vaithiyanathan Dhandapani, Baljit Kaur:
Architectural analysis of 1-D to 2-D array conversion of priority encoder. Int. J. Syst. Assur. Eng. Manag. 14(5): 1726-1737 (2023) - 2021
- [j6]Suruchi Sharma, Rikmantra Basu, Baljit Kaur:
Interface trap charges associated reliability analysis of Si/Ge heterojunction dopingless TFET. IET Circuits Devices Syst. 15(5): 424-433 (2021) - [c10]Baljit Kaur, Jhilik Bhattacharya:
A Hybrid Approach for Scene Matching used for Autonomous vehicles. ICC Workshops 2021: 1-6 - [c9]Suruchi Sharma, Rikmantra Basu, Baljit Kaur:
DC and linearity performance of a novel Si0.6Ge0.4/Ge Dopingless Tunnel FET for ultra-low voltage applications. ISDCS 2021: 1-5 - [c8]Suruchi Sharma, Rikmantra Basu, Baljit Kaur:
Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations. ISQED 2021: 314 - 2020
- [j5]Suruchi Sharma, Baljit Kaur:
Performance investigation of asymmetric double-gate doping less tunnel FET with Si/Ge heterojunction. IET Circuits Devices Syst. 14(5): 695-701 (2020) - [c7]Sneha Bharti, Suruchi Sharma, Abhishek Verma, Manisha Bharti, Baljit Kaur:
Performance analysis of Pocket Doped Junction-Less TFET. ISDCS 2020: 1-4 - [c6]Abhishek Verma, Suruchi Sharma, Sneha Bharti, Manisha Bharti, Baljit Kaur:
Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications. ISDCS 2020: 1-6
2010 – 2019
- 2019
- [j4]Baljit Kaur, Jhilik Bhattacharya:
A convolutional feature map-based deep network targeted towards traffic detection and classification. Expert Syst. Appl. 124: 119-129 (2019) - [j3]Baljit Kaur, Jhilik Bhattacharya:
Scene perception system for visually impaired based on object detection and classification using multimodal deep convolutional neural network. J. Electronic Imaging 28(1): 013031 (2019) - 2018
- [i2]Baljit Kaur, Jhilik Bhattacharya:
A Convolutional Feature Map based Deep Network targeted towards Traffic Detection and Classification. CoRR abs/1805.08769 (2018) - [i1]Baljit Kaur, Jhilik Bhattacharya:
A scene perception system for visually impaired based on object detection and classification using multi-modal DCNN. CoRR abs/1805.08798 (2018) - 2016
- [j2]Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand:
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53: 45-55 (2016) - 2015
- [c5]Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand:
Timing model for two stage buffer and its application in ECSM characterization. VDAT 2015: 1-6 - 2014
- [j1]Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand:
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3407-3415 (2014) - 2013
- [c4]Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand:
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED 2013: 665-669 - 2012
- [c3]Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand:
An accurate current source model for CMOS based combinational logic cell. ISQED 2012: 561-565 - [c2]Baljit Kaur, Manoj Kumar Majumder:
Novel VLSI architecture for two-dimensional radon transform computations. RAIT 2012: 570-575 - 2011
- [c1]Sandeep Miryala, Baljit Kaur, Bulusu Anand, Sanjeev Manhas:
Efficient nanoscale VLSI standard cell library characterization using a novel delay model. ISQED 2011: 458-463
Coauthor Index
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