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Journal Articles
- 2021
[j4]David Bol
, Maxime Schramme, Ludovic Moreau, Pengcheng Xu, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre:
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. IEEE J. Solid State Circuits 56(7): 2256-2269 (2021)- 2018
- [j3]Romuald Elie, Ludovic Moreau, Dylan Possamaï:
On a Class of Path-Dependent Singular Stochastic Control Problems. SIAM J. Control. Optim. 56(5): 3260-3295 (2018) - 2016
- [j2]Bruno Bouchard, Ludovic Moreau, H. Mete Soner:
Hedging Under an Expected Loss Constraint with Small Transaction Costs. SIAM J. Financial Math. 7(1): 508-551 (2016) - 2011
- [j1]Ludovic Moreau:
Stochastic Target Problems with Controlled Loss in Jump Diffusion Models. SIAM J. Control. Optim. 49(6): 2577-2607 (2011)
Conference and Workshop Papers
- 2021
- [c5]Martin Lefebvre, Ludovic Moreau, Rémi Dekimpe, David Bol:
A 0.2-to-3.6TOPS/W Programmable Convolutional Imager SoC with In-Sensor Current-Domain Ternary-Weighted MAC Operations for Feature Extraction and Region-of-Interest Detection. ISSCC 2021: 118-120 - [c4]Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol:
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management. VLSI Circuits 2021: 1-2 - 2019
- [c3]Ludovic Moreau, Rémi Dekimpe, David Bol:
A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. ISCAS 2019: 1-4 - [c2]David Bol, Maxime Schramme, Ludovic Moreau, Thomas Haine, Pengcheng Xu, Charlotte Frenkel, Remi Dekimpe, François Stas, Denis Flandre:
A 40-to-80MHz Sub-4μW/MHz ULV Cortex-M0 MCU SoC in 28nm FDSOI With Dual-Loop Adaptive Back-Bias Generator for 20μs Wake-Up From Deep Fully Retentive Sleep Mode. ISSCC 2019: 322-324 - 2017
- [c1]Thomas Haine, Quoc-Khoi Nguyen, François Stas, Ludovic Moreau, Denis Flandre, David Bol:
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation. ESSCIRC 2017: 312-315
Coauthor Index
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