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ORCIDOliver Schliebusch
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2000 – 2009
- 2007
[b1]Oliver Schliebusch, Heinrich Meyr, Rainer Leupers:
Optimized ASIP synthesis from architecture description language models. RWTH Aachen University, Germany, Kluwer 2007, ISBN 978-1-4020-5685-7, pp. I-XIV, 1-193- 2006
- [c11]Luca Fanucci, Michele Cassiano, Sergio Saponara
, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum 2006: 233-238 - [c10]Anupam Chattopadhyay, B. Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Automatic ADL-based operand isolation for embedded processors. DATE 2006: 600-605 - 2005
- [c9]Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel:
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC 2005: 280-285 - [c8]Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler:
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. ICCD 2005: 193-199 - [c7]Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping 2005: 165-171 - 2004
- [j2]Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr:
A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1625-1639 (2004) - [c6]Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl:
RTL Processor Synthesis for Architecture Exploration and Implementation. DATE 2004: 156-160 - 2003
- [c5]Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr:
Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC 2003: 262-267 - [c4]Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl:
Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE 2003: 10966-10973 - 2002
- [c3]Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann:
A universal technique for fast and flexible instruction-set architecture simulation. DAC 2002: 22-27 - [c2]Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
Architecture Implementation Using the Machine Description Language LISA. ASP-DAC/VLSI Design 2002: 239-244 - 2001
- [j1]Andreas Hoffmann, Tim Kogel, Achim Nohl, Gunnar Braun, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink, Heinrich Meyr:
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1338-1354 (2001) - [c1]Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr:
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. ICCAD 2001: 625-630
Coauthor Index
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