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ORCIDAshis Kumar Mal
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2020 – today
- 2024
[j17]Anu Samanta, Indranil Hatai, Ashis Kumar Mal:
A Survey on Hardware Accelerator Design of Deep Learning for Edge Devices. Wirel. Pers. Commun. 137(3): 1715-1760 (2024)- 2023
- [j16]Amrita Mukherjee
, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal:
Performance of Novel Adaptive Schemes for Cognitive Full-Duplex Relaying-Based Downlink Cooperative NOMA. IEEE Trans. Wirel. Commun. 22(5): 3161-3179 (2023) - 2022
- [j15]Biswajit Ghosh, Aniruddha Chandra, Ashis Kumar Mal:
Fuzzy Logic-Based Energy-Optimal Collinear DF Relay Placement in Two-Hop η -μ Fading Channel. Int. J. Wirel. Inf. Networks 29(2): 167-179 (2022) - [j14]Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal:
Cooperative Mode Switching-Based Cognitive NOMA With Transmit Antenna and User Selection. IEEE Trans. Signal Inf. Process. over Networks 8: 932-945 (2022) - 2021
- [j13]Debabrata Bej, Shubhranil Chakraborty, Sekh Arif Mahammad, Ashis Kumar Mal:
A cost-effective alertness-rating tool to enable situational awareness among on-duty static security guards in Covid-19 pandemic. J. Reliab. Intell. Environ. 7(4): 341-353 (2021) - [c16]Amrita Mukherjee, Pratik Chakraborty, Shankar Prakriya, Ashis Kumar Mal:
Performance of an Adaptive Cooperative NOMA Scheme with Transmit Antenna Selection. ANTS 2021: 296-301 - 2020
- [j12]R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra:
Time-Domain Smart Temperature Sensor Using Current Starved Inverters and Switched Ring Oscillator-Based Time-to-Digital Converter. Circuits Syst. Signal Process. 39(4): 1751-1769 (2020) - [j11]Sumalya Ghosh, Bishnu Prasad De, Kanchan Baran Maji, Rajib Kar, Durbadal Mandal, Ashis Kumar Mal:
Optimal Design of Ultra-Low-Power 2.4 GHz LNA for IEEE 802.15.4/Bluetooth Applications. J. Circuits Syst. Comput. 29(16): 2050261:1-2050261:19 (2020) - [c15]Ayut Ghosh, Arka Prava Roy, Ramapati Patra, Ashis Kumar Mal, Hemanta Kumar Mondal:
An Efficient NoC-based ANN Framework for Epileptic Seizure Recognition. iSES 2020: 75-80
2010 – 2019
- 2019
- [j10]Debabrata Bej, Subhajit Rakshit, Ashis Kumar Mal, Rajat Mahapatra:
A cost-effective system for triggering alarm to distracted drivers/ nurses. Comput. Electr. Eng. 76: 24-39 (2019) - [j9]Sumalya Ghosh, Bishnu Prasad De, Rajib Kar, Durbadal Mandal, Ashis Kumar Mal:
Optimal design of complementary metal-oxide-semiconductor analogue circuits: An evolutionary approach. Comput. Electr. Eng. 80 (2019) - [j8]Sumalya Ghosh, Bishnu Prasad De, Rajib Kar, Ashis Kumar Mal:
Symbiotic organisms search algorithm for optimal design of CMOS two-stage op-amp with nulling resistor and robust bias circuit. IET Circuits Devices Syst. 13(5): 679-688 (2019) - [j7]Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal, Sumalya Ghosh:
Fast and optimised design of a differential VCO using symbolic technique and multi objective algorithms. IET Circuits Devices Syst. 13(8): 1187-1195 (2019) - [j6]R. S. S. M. R. Krishna, Ashis Kumar Mal, Rajat Mahapatra:
All MOS noise-shaped time-mode temperature sensor. Integr. 65: 74-80 (2019) - 2018
- [j5]Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal:
Performance enhancement of a VCO using symbolic modelling and optimisation. IET Circuits Devices Syst. 12(2): 196-202 (2018) - 2017
- [j4]Biswajit Ghosh, Aniruddha Chandra, Ashis Kumar Mal:
Optimal Location of Energy Efficient DF Relay Node in κ - μ Fading Channel. Wirel. Pers. Commun. 96(1): 669-682 (2017) - 2015
- [j3]Jaydeep Howlader, Ashis Kumar Mal:
Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment. Secur. Commun. Networks 8(18): 3415-3440 (2015) - [c14]Subhrabrata Choudhury, Vivek Nair, Jaydeep Howlader, B. Choudhury, Ashis Kumar Mal:
An integrated routing and offset-time adaptation scheme for OBS network. ICDCN 2015: 28:1-28:10 - [c13]Saurav Mandal, Ashis Kumar Mal:
Analysis of resistive load ring oscillator. ReTIS 2015: 471-474 - 2014
- [i1]Jaydeep Howlader, Sanjit Kumar Roy, Ashis Kumar Mal:
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment. IACR Cryptol. ePrint Arch. 2014: 189 (2014) - 2013
- [c12]Jaydeep Howlader, Sanjit Kumar Roy, Ashis Kumar Mal:
Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment. ICISC 2013: 418-434 - [c11]Rishi Todani, Ashis Kumar Mal:
A power efficient and digitally assisted CMOS complementary telescopic amplifier with wide input common mode range. ISQED 2013: 416-421 - 2012
- [j2]Subhrabrata Choudhury, Vivek Nair, Ashis Kumar Mal:
Routing Scheme for OBS Networks. JOCN 4(10): 799-811 (2012) - [c10]Jaydeep Howlader, Jayanta Kar, Ashis Kumar Mal:
Coercion Resistant MIX for Electronic Auction. ICISS 2012: 238-248 - 2010
- [j1]Subhrabrata Choudhury, Gargi Chakraborty, Ashish Kumar Mal:
Impact of Burst Assembly Algorithms on Data Loss in OBS Networks Under Time-Correlated Traffic Input. JOCN 2(12): 1063-1076 (2010) - [c9]Ashis Kumar Mal, Om Prakash Hari, Rishi Todani, Anindya Sundar Dhar:
Design of DXT architecture using current switched integrator. APCCAS 2010: 576-579 - [c8]Rajib Kar, Vikas Maheshwari, Md. Maqbool, Ashish Kumar Mal, A. K. Bhattacharjee:
A Closed Form Slew Evaluation Approach Using Burr's Distribution Function for High Speed On-Chip RC Interconnects. BAIP 2010: 71-75
2000 – 2009
- 2008
- [c7]Shainky Gupta, Anuran Chattaraj, Rajib Kar, Ashish Kumar Mal:
Interconnect Slew Metric Using Nakagami-M Distribution. ICETET 2008: 400-403 - [c6]Rajib Kar, Anuran Chattaraj, Aniruddha Chandra, Ashis Kumar Mal, A. K. Bhattacharjee:
Delay Estimation for On-Chip VLSI Interconnect using Weibull Distribution Function. ICIIS 2008: 1-3 - 2004
- [c5]Ashis Kumar Mal, Arindam Basu:
A generalized analog architecture for DCT, DST and its inverse. ICASSP (5) 2004: 261-264 - [c4]Arindam Basu, Ashis Kumar Mal, Anindya Sundar Dhar:
Digital controlled analog architecture for DCT and DST using capacitor switching. ISCAS (2) 2004: 309-312 - [c3]Ashis Kumar Mal, Arindam Basu, Anindya Sundar Dhar:
Sampled analog architecture for DCT and DST. ISCAS (2) 2004: 825-828 - [c2]Ashis Kumar Mal, Anindya Sundar Dhar:
Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. VLSI Design 2004: 666-669 - 2003
- [c1]Ashis Kumar Mal, Anindya Sundar Dhar:
Analog sampled data architecture for discrete Hartley transform for prime N. ICECS 2003: 152-155
Coauthor Index
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last updated on 2024-08-18 00:32 CEST by the dblp team
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