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ORCIDBo Yang 0004
Person information
- affiliation: Synopsys, Inc., Mountain View, CA, USA
- affiliation: Design Algorithm Laboratory, Inc., Japan
- affiliation (PhD 2009): University of Kitakyushu, School of Environmental Engineering, Fukuoka, Japan
Other persons with the same name
- Bo Yang — disambiguation page
- Bo Yang 0001
![[0000-0001-7961-853X]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-7961-853X")
— University of Jinan, Shandong Provincial Key Laboratory of Network Based Intelligent Computing, China - Bo Yang 0002 — Jilin University, College of Computer Science and Technology, Key Laboratory of Symbolic Computation and Knowledge Engineering, Changchun, China
- Bo Yang 0003 — Shaanxi Normal University, School of Computer Science, Xi'an, China (and 3 more)
- Bo Yang 0005 — Bowie State University
- Bo Yang 0006 — Shanghai Jiao Tong University, Department of Automation, Key Laboratory of System Control and Information Processing, Shanghai, China (and 1 more)
- Bo Yang 0007 — Beijing University of Posts and Telecommunications
- Bo Yang 0008 — Samsung (and 2 more)
- Bo Yang 0009 (aka: Tony Bo Yang) — University of Turku
- Bo Yang 0010 — NVIDIA (and 1 more)
- Bo Yang 0011 — University of Electronic Science and Technology of China, School of Computer Science and Engineering, Chengdu (and 1 more)
- Bo Yang 0012 — Chongqing University of Science and Technology, College of Electrical and Information Engineering, China
- Bo Yang 0013 — IBM China Research Laboratory (and 1 more)
- Bo Yang 0016 — Renmin University of China
- Bo Yang 0017 — Université Michel de Montaigne
- Bo Yang 0018 — Texas Tech University (and 1 more)
- Bo Yang 0019 — Southeast University, School of Instrument Science and Engineering, Nanjing, China (and 1 more)
- Bo Yang 0020 — University of Calgary, Department of Chemical and Petroleum Engineering, AB, Canada
- Bo Yang 0021 — Hunan University, National Supercomputing Center in Changsha, China
- Bo Yang 0022 — University of Electronic Science and Technology of China, School of Automation Engineering, Chengdu, China (and 1 more)
- Bo Yang 0023 — National University of Defense Technology, Department of Computer Sciences, Changsha, China
- Bo Yang 0024 — Nanjing Agricultural University, Department of Information Management, China
- Bo Yang 0025 — Southwest University, College of Electronic and Information Engineering, Chongqing, China
- Bo Yang 0026 — Chinese Academy of Sciences, Institute of Computing Technology, SKL Computer Architecture, Beijing, China (and 1 more)
- Bo Yang 0027 — The Hong Kong Polytechnic University, Department of Computing, HKSAR (and 2 more)
- Bo Yang 0028 — Beijing Forestry University, School of Information Science and Technology, China
- Bo Yang 0029 — Southeast University, Jiangsu Key Laboratory of Urban ITS, Nanjing, China
- Bo Yang 0030 — University of Paris-Sud, Orsay, France
- Bo Yang 0031 — Jiang Xi University of Finance and Economics, School of Information Management, Nanchang, China
- Bo Yang 0032 — Inner Mongolia University, College of Computer Science, Hohhot, China (and 1 more)
- Bo Yang 0033 — University of Central Florida, FL, USA (and 1 more)
- Bo Yang 0034 — Tongji University, Key Laboratory of Embedded System and Service Computing, Shanghai, China
- Bo Yang 0035 — Northwestern Polytechnical University, School of Computer Science, Xi'an, China (and 3 more)
- Bo Yang 0036 — Hunan Institute of Science and Technology, College of Information and Communication Engineering, Yueyang, China (and 1 more)
- Bo Yang 0038 — Harbin Engineering University, College of Automation, China
- Bo Yang 0039 — Xi'an Research Institute of High Technology, Department of Control Engineering, China
- Bo Yang 0040 — Beihang University, School of Electronic and Information Engineering, Beijing, China
- Bo Yang 0041 — Xi'an Polytechnic University, School of Computer Science, Shaanxi Key Laboratory of Clothing Intelligence, China (and 1 more)
- Bo Yang 0042 — Chongqing University, State Key Laboratory of Mechanical Transmission, China
- Bo Yang 0043 — Northwest Normal University, Institute of Computer Science and Engineering, Lanzhou, China
- Bo Yang 0044 — University of Tokyo, Institute of Industrial Science, Japan
- Bo Yang 0045 — Alibaba Group, Hangzhou, China
- Bo Yang 0046 — Kunming University of Science and Technology, Faculty of Electric Power Engineering, China (and 1 more)
- Bo Yang 0047 — Xidian University, School of Artificial Intelligence, Xi'an, China
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Journal Articles
- 2018
[j8]Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake:
Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Design Autom. Electr. Syst. 23(4): 47:1-47:17 (2018)- 2016
- [j7]Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang:
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. ACM Trans. Design Autom. Electr. Syst. 21(3): 45:1-45:21 (2016) - 2013
- [j6]Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake:
Structured Analog Circuit and Layout Design with Transistor Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2475-2486 (2013) - [j5]Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake:
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2487-2498 (2013) - 2012
- [j4]Bo Liu, Bo Yang, Shigetoshi Nakatake:
Layout-Aware Variability Characterization of CMOS Current Sources. IEICE Trans. Electron. 95-C(4): 696-705 (2012) - 2009
- [j3]Bo Yang, Shigetoshi Nakatake:
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3052-3060 (2009) - [j2]Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3103-3110 (2009) - 2008
- [j1]Bo Yang, Hiroshi Murata, Shigetoshi Nakatake:
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 542-549 (2008)
Conference and Workshop Papers
- 2016
- [c15]Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen:
Twin-row-style for MOS analog layout. ICECS 2016: 141-144 - [c14]Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang:
Routability of twisted common-centroid capacitor array under signal coupling constraints. MWSCAS 2016: 1-4 - 2013
- [c13]Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake:
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ACM Great Lakes Symposium on VLSI 2013: 315-316 - [c12]Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake:
A comparator energy model considering shallow trench isolation stress by geometric programming. ISQED 2013: 585-590 - 2012
- [c11]Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue:
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. ISCAS 2012: 938-941 - [c10]Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake:
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. ISQED 2012: 464-469 - [c9]Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake:
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. ISQED 2012: 656-662 - 2011
- [c8]Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake:
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. ACM Great Lakes Symposium on VLSI 2011: 247-252 - [c7]Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. ISQED 2011: 525-532 - 2010
- [c6]Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake:
D-A converter based variation analysis for analog layout design. ASP-DAC 2010: 843-848 - [c5]Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake:
Structured analog circuit design and MOS transistor decomposition for high accuracy applications. ICCAD 2010: 721-728 - [c4]Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake:
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. ISCAS 2010: 929-932 - 2009
- [c3]Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake:
STI stress aware placement optimization based on geometric programming. ACM Great Lakes Symposium on VLSI 2009: 209-214 - [c2]Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake:
Incremental buffer insertion and module resizing algorithm using geometric programming. ACM Great Lakes Symposium on VLSI 2009: 413-416 - 2008
- [c1]Bo Yang, Shigetoshi Nakatake, Hiroshi Murata:
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. ISQED 2008: 617-620
Coauthor Index
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