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2020 – today
- 2022
[c9]Bingru Wu, Diandian Zhang, Tao Ma, Ruixuan Jiang, Hanming Gao, Guanghui Liu:
A High-Sensitivity Wake-up Receiver Using Tunnel Diode for ISM Band. ICCT 2022: 1493-1496- 2021
- [j5]Diandian Zhang, Yan Liu, Zhuowei Wang, Depei Wang
:
OCR with the Deep CNN Model for Ligature Script-Based Languages like Manchu. Sci. Program. 2021: 5520338:1-5520338:9 (2021)
2010 – 2019
- 2014
- [c8]Stefan Schürmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
Improving ESL power models using switching activity information from timed functional models. SCOPES 2014: 89-97 - 2013
- [j4]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Efficient Implementation of Application-Aware Spinlock Control in MPSoCs. Int. J. Embed. Real Time Commun. Syst. 4(1): 64-84 (2013) - [c7]Stefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang:
Creation of ESL power models for communication architectures using automatic calibration. DAC 2013: 58:1-58:58 - 2012
- [c6]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Application-aware spinlock control using a hardware scheduler in MPSoC platforms. ISSoC 2012: 1-6 - 2011
- [j3]Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers:
Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis. Int. J. Embed. Real Time Commun. Syst. 2(3): 1-20 (2011) - 2010
- [c5]Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Optimized communication architecture of MPSoCs with a hardware scheduler: A system view. SoC 2010: 163-168
2000 – 2009
- 2009
- [j2]Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Integrated verification approach during ADL-driven processor design. Microelectron. J. 40(7): 1111-1123 (2009) - [c4]David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rudolf Mathar:
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. CHES 2009: 254-271 - [c3]Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid:
Task management in MPSoCs: An ASIP approach. ICCAD 2009: 587-594 - [i1]David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr:
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. 2009: 56 (2009) - 2008
- [j1]Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
Power-efficient Instruction Encoding Optimization for Various Architecture Classes. J. Comput. 3(3): 25-38 (2008) - 2007
- [c2]Anupam Chattopadhyay, Diandian Zhang, David Kammler, Ernst Martin Witte:
Power-efficient Instruction Encoding Optimization for Embedded Processors. VLSI Design 2007: 595-600 - 2006
- [c1]Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping 2006: 110-118
Coauthor Index
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