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2020 – today
- 2020
[j3]Andreas Voigt
, Jörg Schreiter, Philipp Frank, Cesare Pini, Christian Mayr, Andreas Richter:
Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1635-1648 (2020)- [j2]Sebastian Höppner, Holger Eisenreich, Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Jörg Schreiter, Thorsten Riedel, Heiner Bauer, Robert Niebsch, Stephan Scherzer, Thomas Hocker, Stefan Scholze, Stephan Henker, Matthias Nossmann, Ulrich Hensel, Helmut Prengel:
Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2159-2163 (2020) - [c13]Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner:
A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM. COOL CHIPS 2020: 1-3
2010 – 2019
- 2019
- [c12]Sebastian Höppner, Jörg Schreiter, Robert Niebsch, Stephan Scherzer, Ulrich Hensel, Jörg Winkler, Mario Orgis, Holger Eisenreich, Dennis Walter, Uwe Steeb, André Scharfe, Clifford Dmello, Robert Sinkwitz, Heiner Bauer, Alexander Oefelein, Florian Schraut:
How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC. ESSDERC 2019: 66-69 - 2016
- [c11]Sebastian Haas, Oliver Arnold, Benedikt Nöthen, Stefan Scholze, Georg Ellguth, Andreas Dixius, Sebastian Höppner, Stefan Schiefer, Stephan Hartmann, Stephan Henker, Thomas Hocker, Jörg Schreiter, Holger Eisenreich, Jens-Uwe Schlüßler, Dennis Walter, Tobias Seifert, Friedrich Pauls, Mattis Hasler, Yong Chen, Hermann Hensel, Sadia Moriam, Emil Matús, Christian Mayr, René Schüffny, Gerhard P. Fettweis:
An MPSoC for energy-efficient database query processing. DAC 2016: 112:1-112:6
2000 – 2009
- 2004
- [c10]Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny:
Pulse coupled neural networks with adaptive synapses for image segmentation. ARCS Workshops 2004: 275-282 - [c9]Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny:
Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. Image Processing: Algorithms and Systems 2004: 290-296 - [c8]Daniel Matolin, Jörg Schreiter, Stefan Getzlaff, René Schüffny:
An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. PARELEC 2004: 51-55 - 2003
- [j1]Achim Graupner, Jörg Schreiter, Stefan Getzlaff, René Schüffny:
CMOS image sensor with mixed-signal processor array. IEEE J. Solid State Circuits 38(6): 948-957 (2003) - [c7]Riad Stefo, Jörg Schreiter, Jens-Uwe Schluessler, René Schüffny:
High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications. FPT 2003: 28-34 - 2002
- [c6]Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny:
An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. ICANN 2002: 1293-1298 - [c5]Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, D. Matolini, René Schüffny:
Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity. NNSP 2002: 657-666 - 2001
- [c4]Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny:
A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. ISCAS (4) 2001: 486-489 - [c3]Jörg Krupar, Rico Srowik, Jörg Schreiter, Achim Graupner, René Schüffny, Udo Jörges:
Minimizing charge injection errors in high-precision, high-speed SC-circuits. ISCAS (1) 2001: 727-730 - [c2]Achim Graupner, Stefan Getzlaff, Jörg Schreiter, René Schüffny:
A vision device for image processing. SIP 2001: 78-83
1990 – 1999
- 1999
- [c1]Jörg Schreiter, Rico Srowik, Achim Graupner, Stefan Getzlaff, René Schüffny:
Design of parallel preprocessing image sensors. KES 1999: 393-396
Coauthor Index
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