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2010 – 2019
- 2014
[j7]Aart J. de Geus:
The Greatest "Tech-Onomic Push-Pull" in Human History. IEEE Des. Test 31(2): 9-12 (2014)
2000 – 2009
- 2007
- [j6]Aart J. de Geus:
A. Richard Newton: Technologist with a Mission. IEEE Des. Test Comput. 24(1): 6-7 (2007) - [c11]Francine Bacchini, Gregory S. Spirakis, Juan Antonio Carballo, Kurt Keutzer, Aart J. de Geus, Fu-Chieh Hsu, Kazu Yamada:
Megatrends and EDA 2017. DAC 2007: 21-22 - 2005
- [c10]Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy:
Differentiate and deliver: leveraging your partners. DAC 2005: 1 - 2004
- [c9]Robert Dahlberg, Kurt Keutzer, R. Bingham, Aart J. de Geus, Walden C. Rhines:
EDA: this is serious business. DAC 2004: 1 - 2002
- [c8]Aart J. de Geus:
Electronic Industry on Fire: How to Survive and Thrive. ASP-DAC/VLSI Design 2002: 6 - 2000
- [c7]Aart J. de Geus:
Slap it Together and Ship it! ISQED 2000: 23-24
1990 – 1999
- 1994
- [c6]Joseph B. Costello, Walden C. Rhines, Aart J. de Geus, Alain Hanover, Doug Fairbairn, Rick Carlson, Ronald Collett:
Executive Perspective and Vision of the Future of EDA (Panel). DAC 1994: 48 - [c5]Aart J. de Geus:
Test: The New Value-Added Field. ITC 1994: 12 - 1992
- [j5]Allen Dewey, Aart J. de Geus:
VHDL: Toward a Unified View of Design. IEEE Des. Test Comput. 9(2): 8-17 (1992) - [c4]Aart J. de Geus:
High Level Design: A Design Vision for the 90's. ICCD 1992: 8
1980 – 1989
- 1987
- [j4]Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory:
Testability-Driven Random Test-Pattern Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(6): 1082-1087 (1987) - 1986
- [j3]David Hightower, Aart J. de Geus, Patrick Fasang, Robert Griffin, Gary Leive:
Computer-Aided-Design Research at the GE Microelectronics Center. IEEE Des. Test 3(5): 49-56 (1986) - [j2]Karen A. Bartlett, William W. Cohen, Aart J. de Geus, Gary D. Hachtel:
Synthesis and Optimization of Multilevel Logic under Timing Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5(4): 582-596 (1986) - [c3]Aart J. de Geus:
Logic synthesis and optimization benchmarks for the 1986 Design Automation Conference. DAC 1986: 78 - [c2]David Gregory, Karen A. Bartlett, Aart J. de Geus, Gary D. Hachtel:
SOCRATES: a system for automatically synthesizing and optimizing combinational logic. DAC 1986: 79-85 - 1985
- [j1]Aart J. de Geus, William W. Cohen:
A Rule-Based System for Optimizing Combinational Logic. IEEE Des. Test 2(4): 22-32 (1985) - 1984
- [c1]Aart J. de Geus, J. B. Reed, M. Rekhson, G. Wikle:
IDA: Interconnect delay analysis for integrated circuits. DAC 1984: 536-541
Coauthor Index
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