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ORCIDÉricles Sousa
Person information
- affiliation (PhD 2018): Friedrich-Alexander University (FAU), Department of Computer Science, Erlangen, Germany
- affiliation: State University of Campinas (UNICAMP), School of Electrical and Computer Engineering, Campinas, Brazil
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Books and Theses
- 2018
[b1]Éricles Sousa:
Memory and interface architectures for invasive tightly coupled processor arrays = Speicher- und Schnittstellenarchitekturen für invasive eng gekoppelte Prozessorfelder. University of Erlangen-Nuremberg, Germany, 2018, pp. 1-159
Journal Articles
- 2021
- [j4]Marcel Brand
, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
*-Predictable MPSoC execution of real-time control applications using invasive computing. Concurr. Comput. Pract. Exp. 33(14) (2021) - 2017
- [j3]Heba Khdr, Santiago Pagani, Éricles Sousa, Vahid Lari, Anuj Pathania, Frank Hannig, Muhammad Shafique, Jürgen Teich, Jörg Henkel:
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores. IEEE Trans. Computers 66(3): 488-501 (2017) - 2016
- [j2]Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel:
Dark silicon management: an integrated and coordinated cross-layer approach. it Inf. Technol. 58(6): 297-307 (2016) - 2015
- [j1]Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. 61(10): 668-680 (2015)
Conference and Workshop Papers
- 2018
- [c12]Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study. ASAP 2018: 1-9 - 2017
- [c11]Éricles Sousa, Arindam Chakraborty, Alexandru Tanase, Frank Hannig, Jürgen Teich:
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays. ReConFig 2017: 1-3 - [c10]Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays. ReConFig 2017: 1-8 - 2015
- [c9]Éricles Sousa, Frank Hannig, Jürgen Teich:
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. IESS 2015: 218-229 - [c8]Éricles Sousa, Frank Hannig, Jürgen Teich, Qingqing Chen, Ulf Schlichtmann:
Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays. SCOPES 2015: 121-124 - 2014
- [c7]Deepak Gangadharan, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich:
Application-driven reconfiguration of shared resources for timing predictability of MPSoC platforms. ACSSC 2014: 398-403 - [c6]Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour:
Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP 2014: 1-8 - [c5]Éricles Sousa:
Resource-aware Computer Vision Algorithms on Heterogeneous MPSoC Architectures. Joint Workshop of the German Research Training Groups in Computer Science 2014: 186 - [c4]Éricles Sousa, Deepak Gangadharan, Frank Hannig, Jürgen Teich:
Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures. DSD 2014: 74-81 - 2013
- [c3]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
Accuracy and performance analysis of Harris Corner computation on tightly-coupled processor arrays. DASIP 2013: 88-95 - [c2]Éricles Rodrigues Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich:
A prototype of an adaptive computer vision algorithm on MPSoC architecture. DASIP 2013: 353-354 - 2011
- [c1]Éricles Rodrigues Sousa, Luis Meloni:
An Analytical Model Proposed for Evaluating Efficiency of Partitioning Code in Hybrid Architectures Based on DSP and FPGA. HPCC 2011: 493-499
Coauthor Index
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