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Chinmay K. Maiti

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affiliation: Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology (IIT), Kharagpur, India

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2010 – 2019

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2016
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Tapas Kumar Maiti, Chinmay K. Maiti:
Reduction of Self-heating effect in LDMOS devices. CoRR abs/1608.07233 (2016)
2013
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Chinmay K. Maiti, Ananda Maiti:
Enhancing microelectronics education using online semiconductor technology CAD laboratory. FIE 2013: 866-871
2012
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Ananda Maiti, Subhasis Mahata, Chinmay K. Maiti:
RF Laboratory for Engineering Education. T4E 2012: 208-211
2011
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Enrique Miranda, C. Mahata, Tanmoy Das, Chinmay K. Maiti:
An extension of the Curie-von Schweidler law for the leakage current decay in MIS structures including progressive breakdown. Microelectron. Reliab. 51(9-11): 1535-1539 (2011)
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Ananda Maiti, Anindya Maiti, Chinmay K. Maiti:
Online technology CAD laboratory for microelectronics education. EUROCON 2011: 1-4
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Chinmay K. Maiti, Subhasis Mahata, Ananda Maiti:
Design and Development of a Cost-Effective Online Electronic Circuits Laboratory. T4E 2011: 221-224
2010
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Subhasis Mahata, Ananda Maiti, Chinmay K. Maiti:
Cost-effectiveweb-based electronics laboratory using NI MultiSim, LabVIEW and ELVIS II. T4E 2010: 242-243

2000 – 2009

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2009
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Chinmay K. Maiti, S. C. Pandey, Ananda Maiti, Tapas Kumar Maiti:
Online MOS Capacitor Characterization in LabVIEW Environment. Int. J. Online Eng. 5(S1): 57-60 (2009)
2008
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M. K. Bera, Chinmay K. Maiti:
Reliability of ultra thin ZrO₂ films on strained-Si. Microelectron. Reliab. 48(5): 682-692 (2008)
2005
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Anirban Saha, S. Chattopadhyay, G. K. Dalapati, S. K. Nandi, Chinmay K. Maiti:
An investigation of electrical and structural properties of Ni-germanosilicided Schottky diode. Microelectron. Reliab. 45(7-8): 1154-1160 (2005)
2000
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B. Senapati, Chinmay K. Maiti, Nirmal B. Chakrabarti:
Silicon Heterostructure Devices for RF Wireless Communication. VLSI Design 2000: 488-491

1990 – 1999

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1992
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Chinmay K. Maiti:
Optimization Of Cut-off Frequency Of High Speed Bipolar Transistors Fabricated In The N-well Of A C-mos Process At Low Temperature. VLSI Design 1992: 332-333

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