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ORCIDBetul Buyukkurt
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Journal Articles
- 2010
[j3]Betul Buyukkurt, John Cortes, Jason R. Villarreal, Walid A. Najjar
:
Impact of high-level transformations within the ROCCC framework. ACM Trans. Archit. Code Optim. 7(4): 17:1-17:36 (2010)- 2008
- [j2]Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar:
A Compiler Intermediate Representation for Reconfigurable Fabrics. Int. J. Parallel Program. 36(5): 493-520 (2008) - [j1]Zhi Guo, Walid A. Najjar, Betul Buyukkurt:
Efficient hardware code generation for FPGAs. ACM Trans. Archit. Code Optim. 5(1): 6:1-6:26 (2008)
Conference and Workshop Papers
- 2008
- [c5]Betul Buyukkurt, Walid A. Najjar:
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. FPL 2008: 655-658 - 2006
- [c4]Betul Buyukkurt, Zhi Guo, Walid A. Najjar:
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. ARC 2006: 401-412 - [c3]Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar:
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. ARC 2006: 413-418 - 2005
- [c2]Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs. DATE 2005: 112-117 - 2004
- [c1]Zhi Guo, Betul Buyukkurt, Walid A. Najjar:
Input data reuse in compiling window operations onto reconfigurable hardware. LCTES 2004: 249-256
Informal and Other Publications
- 2007
- [i1]Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs. CoRR abs/0710.4716 (2007)
Coauthor Index
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