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ORCIDYudong Zhang 0006
Person information
- affiliation: Apple Inc., San Diego, SerDes Design Engineer, CA, USA
- affiliation (PhD 2021): Columbia University, Department of electrical engineering, NY, USA
- affiliation: Cisco Systems, Allentown, PA, USA
- affiliation (former): Tsinghua University, Institute of Microelectronics, Beijing, China
Other persons with the same name
- Yudong Zhang (aka: Yu-Dong Zhang) — disambiguation page
- Yudong Zhang 0001
![[0000-0002-4870-1493]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-4870-1493")
(aka: Yu-Dong Zhang 0001, Eugene Yu-Dong Zhang) — University of Leicester, Department of Informatics, UK (and 2 more) - Yudong Zhang 0002 — Xidian University, Department of Electronic Engineering, Science and Technology on Antenna and Microwave Laboratory, China
- Yudong Zhang 0003 — Chinese Academy of Sciences, Key Laboratory on Adaptive Optics, Institute of Optics and Electronics, Chengdu, China
- Yudong Zhang 0004 — Nankai University, Institute of Robotics and Automatic Information System, IRAIS, Tianjin, China
- Yudong Zhang 0005 — University of Science and Technology of China, USTC, Suzhou Institute for Advanced Research, Suzhou, China
- Yudong Zhang 0007 — University of Science and Technology, School of Automation and Electrical Engineering, Beijing, China (and 1 more)
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2020 – today
- 2022
[j4]Zhaowen Wang, Yudong Zhang, Yuka Onizuka, Peter R. Kinget:
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL. IEEE J. Solid State Circuits 57(6): 1776-1787 (2022)- [j3]Yudong Zhang, Zhaowen Wang, Peter R. Kinget:
Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3074-3082 (2022) - 2021
- [c2]Zhaowen Wang, Yudong Zhang, Yuka Onizuka, Peter R. Kinget:
11.4 A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links. ISSCC 2021: 186-188
2010 – 2019
- 2018
- [j2]Tanbir Haque, Matthew Bajor, Yudong Zhang, Jianxun Zhu, Zarion A. Jacobs, Blayne Kettlewell, John Wright, Peter R. Kinget:
A Reconfigurable Architecture Using a Flexible LO Modulator to Unify High-Sensitivity Signal Reception and Compressed-Sampling Wideband Signal Detection. IEEE J. Solid State Circuits 53(6): 1577-1591 (2018) - 2017
- [c1]Yudong Zhang, Xiaofeng Liu, Woogeun Rhee, Hanjun Jiang, Zhihua Wang:
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS. ISCAS 2017: 1-4 - 2015
- [j1]Yudong Zhang, Woogeun Rhee, Taeik Kim, Hojin Park, Zhihua Wang:
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 62-II(8): 736-740 (2015)
Coauthor Index
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