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S. Lakshmanachari

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2024
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S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Inapudi Vasavi, Vallabhuni Vijay, Chandra Shaker Pittala:
1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages. Int. J. Syst. Assur. Eng. Manag. 15(3): 950-956 (2024)
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S. Lakshmanachari, Sadulla Shaik, G. S. R. Satyanarayana, Vallabhuni Vijay, Chandra Shaker Pittala, K. Indira, S. Swathi:
Design and analysis of a novel compact quaternary adder. Int. J. Syst. Assur. Eng. Manag. 15(7): 3076-3087 (2024)

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