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Journal Articles
- 2002
[j1]Don Weiss, John J. Wuu, Victor Chin:
The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor. IEEE J. Solid State Circuits 37(11): 1523-1529 (2002)
Conference and Workshop Papers
- 2024
- [c5]Alan Smith, Eric Chapman, Chintan Patel, Raja Swaminathan, John J. Wuu, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh McIntyre, Ramon Mangaser:
11.1 AMD InstinctTM MI300 Series Modular Chiplet Package - HPC and AI Accelerator for Exa-Class Systems. ISSCC 2024: 490-492 - [c4]Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan:
AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. VLSI Technology and Circuits 2024: 1-2 - 2022
- [c3]John J. Wuu, Rahul Agarwal, Michael Ciraula, Carl Dietz, Brett Johnson, Dave Johnson, Russell Schreiber, Raja Swaminathan, Will Walker, Samuel Naffziger:
3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. ISSCC 2022: 428-429 - 2011
- [c2]Don Weiss, Michael Dreesen, Michael Ciraula, Carson Henrion, Chris Helt, Ryan Freese, Tommy Miles, Anita Karegar, Russell Schreiber, Bryan Schneller, John J. Wuu:
An 8MB level-3 cache in 32nm SOI with column-select aliasing. ISSCC 2011: 258-260 - 2009
- [c1]Anant Singh, Michael Ciraula, Don Weiss, John J. Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David E. Fisch, Philippe Graber, Michel Bron:
A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. ISSCC 2009: 460-461
Coauthor Index
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