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ORCIDJohn Lee 0002
Person information
- affiliation: University of California at Los Angeles, CA, USA
Other persons with the same name
- John Lee — disambiguation page
- John Lee 0001
![[0000-0003-2505-2678]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-2505-2678")
(aka: John S. Y. Lee, John Sie Yuen Lee) — City University of Hong Kong, Department of Linguistics and Translation, Hong Kong (and 1 more) - John Lee 0003 — Applied Communication Sciences, Piscataway, NJ, USA (and 1 more)
- John Lee 0004 (aka: John R. Lee 0001) — University of Edinburgh, UK
- John Lee 0005 — University of Illinois at Urbana-Champaign, IL, USA
- John Lee 0006 (aka: John Zhan Yi Lee) — DSO National Laboratories, Singapore, Singapore (and 1 more)
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2010 – 2019
- 2012
[j4]John Lee, Puneet Gupta:
Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment. Found. Trends Electron. Des. Autom. 6(1): 1-120 (2012)- [j3]Santiago Mok, John Lee, Puneet Gupta:
Discrete sizing for leakage power optimization in physical design: A comparative study. ACM Trans. Design Autom. Electr. Syst. 18(1): 15:1-15:11 (2012) - [j2]John Lee, Puneet Gupta:
ECO cost measurement and incremental gate sizing for late process changes. ACM Trans. Design Autom. Electr. Syst. 18(1): 16:1-16:11 (2012) - [c6]John Lee, Puneet Gupta:
Impact of range and precision in technology on cell-based design. ICCAD 2012: 218-225 - [c5]John Lee, Puneet Gupta, Fedor Pikus:
Parametric Hierarchy Recovery in Layout Extracted Netlists. ISVLSI 2012: 332-337 - 2011
- [c4]Jason Cong, John Lee, Guojie Luo:
A unified optimization framework for simultaneous gate sizing and placement under density constraints. ISCAS 2011: 1207-1210 - 2010
- [j1]Jason Cong, Puneet Gupta, John Lee:
Evaluating Statistical Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1750-1762 (2010) - [c3]John Lee, Puneet Gupta:
Incremental gate sizing for late process changes. ICCD 2010: 215-221
2000 – 2009
- 2009
- [c2]Jason Cong, Puneet Gupta, John Lee:
On the futility of statistical power optimization. ASP-DAC 2009: 167-172 - 2008
- [c1]Jason Cong, John Lee, Lieven Vandenberghe:
Robust gate sizing via mean excess delay minimization. ISPD 2008: 10-14
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