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ORCIDTadato Yamagata
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1990 – 1999
- 1999
[j5]Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima
, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada:
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits 34(5): 661-669 (1999)- 1997
- [j4]Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada:
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32(3): 477-482 (1997) - 1996
- [j3]Tadato Yamagata, Hirotoshi Sato, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami:
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond. IEEE J. Solid State Circuits 31(2): 195-201 (1996) - [j2]Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto:
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits 31(4): 586-591 (1996) - 1995
- [j1]Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto:
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits 30(11): 1183-1188 (1995)
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