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Journal Articles
- 2024
[j2]Changxuan Han
, Zhixian Deng, Yiyang Shu, Jun Yin, Pui-In Mak, Xun Luo:
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 120-132 (2024)- 2023
- [j1]Zhixian Deng, Changxuan Han, Yifan Li, Huizhen Jenny Qian, Xun Luo:
A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA. IEEE J. Solid State Circuits 58(3): 647-661 (2023)
Conference and Workshop Papers
- 2024
- [c5]Changxuan Han, Xun Luo:
A -10.1dBm IIP3, 0.3-40GHz Receiver Using Hybrid-Path Band-Selection with Reduced LO Coverage Bandwidth Supporting 480Mb/s 4096-QAM and 7.2Gb/s 64-QAM Modulation. CICC 2024: 1-2 - 2023
- [c4]Jie Zhou, Changxuan Han, Wen Chen, Bingzheng Yang, Xun Luo:
A 71-to-86GHz, 20.4dBm $\mathbf{P}_{\mathbf{out}}$, 6.0dB NF Transceiver with Quadrature Direct-Modulated Transmitter and Reflection-Less Heterodyne Receiver in 40nm CMOS. A-SSCC 2023: 1-3 - [c3]Zhixian Deng, Bingzheng Yang, Wen Chen, Jie Zhou, Changxuan Han, Yifan Li, Yiyang Shu, Xun Luo:
An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR. CICC 2023: 1-2 - [c2]Changxuan Han, Jie Zhou, Zhixian Deng, Yiyang Shu, Xun Luo:
A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS. ISSCC 2023: 374-375 - 2022
- [c1]Zhixian Deng, Huizhen Jenny Qian, Changxuan Han, Yifan Li, Xun Luo:
A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR. CICC 2022: 1-2
Coauthor Index
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