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ORCIDTakafumi Yamaji
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Journal Articles
- 2013
[j18]Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura:
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(5): 1113-1121 (2013)- 2011
- [j17]Takafumi Yamaji, Hiroshi Tanimoto, Junya Matsuno, Tetsuro Itakura:
Harmonic Signal Rejection Schemes of Polyphase Downconverters. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(10): 2308-2317 (2011) - 2010
- [j16]Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 367-374 (2010) - 2008
- [j15]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 454-460 (2008) - [j14]Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 557-560 (2008) - [j13]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. IEICE Trans. Electron. 91-C(6): 887-893 (2008) - 2007
- [j12]Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 365-371 (2007) - 2006
- [j11]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(7): 2003-2008 (2006) - [j10]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid State Circuits 41(7): 1589-1595 (2006) - 2005
- [j9]Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. IEICE Electron. Express 2(15): 429-433 (2005) - [j8]Hiroshi Tanimoto, Ryuta Ito, Takafumi Yamaji:
Nonlinear Analysis of Bipolar Harmonic Mixer for Direct Conversion Receivers. IEICE Trans. Electron. 88-C(6): 1203-1211 (2005) - 2004
- [j7]Tomohiko Ito, Takafumi Yamaji, Daisuke Kurose, Tetsuro Itakura:
Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. IEICE Electron. Express 1(3): 63-68 (2004) - 2003
- [j6]Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi
, Tetsuro Itakura:
A four-input beam-forming downconverter for adaptive antennas. IEEE J. Solid State Circuits 38(10): 1619-1625 (2003) - 2002
- [j5]Osamu Watanabe, Takafumi Yamaji, Tetsuro Itakura, Ichiro Hattori:
A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 286-292 (2002) - [j4]Takafumi Yamaji, Nobuo Kanou, Tetsuro Itakura:
A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range. IEEE J. Solid State Circuits 37(5): 553-558 (2002) - [j3]Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura:
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. IEEE J. Solid State Circuits 37(7): 809-816 (2002) - 1998
- [j2]Takafumi Yamaji, Hiroshi Tanimoto, Hideyuki Kokatsu:
An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter. IEEE J. Solid State Circuits 33(12): 2240-2246 (1998) - 1996
- [j1]Shoji Otaka, Takafumi Yamaji, Ryuichi Fujimoto, Chikau Takahashi, Hiroshi Tanimoto:
A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment. IEEE J. Solid State Circuits 31(1): 30-37 (1996)
Conference and Workshop Papers
- 2012
- [c8]Junya Matsuno, Takafumi Yamaji, Masanori Furuta, Tetsuro Itakura:
All-digital background calibration for time-interleaved ADC using pseudo aliasing signal. ISCAS 2012: 1050-1053 - [c7]Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa:
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. VLSIC 2012: 74-75 - 2011
- [c6]Akihide Sai, Takafumi Yamaji, Tetsuro Itakura:
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop. ISSCC 2011: 98-100 - 2008
- [c5]Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
An area-efficient sampling rate converter using negative feedback technique. ISCAS 2008: 1922-1925 - 2006
- [c4]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. CICC 2006: 501-504 - [c3]Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni:
Balanced 3-phase analog signal processing for radio communications. ISCAS 2006 - 2005
- [c2]Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS. CICC 2005: 747-750 - [c1]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. ESSCIRC 2005: 527-530
Coauthor Index
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