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2020 – today
- 2020
[c8]Mike Bichan, Clifford Ting, Bahram Zand, Jing Wang, Ruslana Shulyzki, James Guthrie, Katya Tyshchenko, Junhong Zhao, Alireza Parsafar, Eric Liu, Aynaz Vatankhahghadim, Shaham Sharifian, Aleksey Tyshchenko, Michael De Vita, Syed Rubab, Sitaraman Iyer, Fulvio Spagna, Noam Dolev:
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol. CICC 2020: 1-4
2010 – 2019
- 2018
- [c7]Shenggao Li
, Fulvio Spagna, Ji Chen, Xiaoqing Wang, Luke Tong, Sujatha Gowder, Wenyan Jia, Roan Nicholson, Sitaraman Iyer, Rui Song, Lily Li, Meng-hung Chen, Amanda Tran, Michael De Vita, Deepar Govindrajan, Marcus Pasquarella, Dave Bradley, Frank Verdico, Matt Duwe, Eric Lee, Michelle Wigton:
A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS. A-SSCC 2018: 5-8 - [c6]Fulvio Spagna:
Clock and data recovery systems. CICC 2018: 1-120 - 2010
- [c5]Fulvio Spagna, Lidong Chen, Mamatha Deshpande, Yongping Fan, Doug Gambetta, Sujatha Gowder, Sitaraman Iyer, Rohit Kumar, Peter Kwok, Renuka Krishnamurthy, Chien-chun Lin, Ravindran Mohanavelu, Roan Nicholson, Jeff Ou, Marcus Pasquarella, Kavitha Prasad, Hendra Rustam, Luke Tong, Amanda Tran, John Wu, Xuguang Zhang:
A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS. ISSCC 2010: 366-367 - [c4]Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran:
Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. ITC 2010: 405-409
2000 – 2009
- 2009
- [c3]Lidong Chen, Xuguang Zhang, Fulvio Spagna:
A Scalable 3.6-to-5.2mW 5-to-10Gb/s 4-tap DFE in 32nm CMOS. ISSCC 2009: 180-181 - 2001
- [c2]Fulvio Spagna:
An improved delay compensation technique for digital clock recovery loops. ICECS 2001: 1395-1398 - 2000
- [c1]Fulvio Spagna:
Phase Locked Loop Using Delay Compensation Techniques. ISCC 2000: 417-423
Coauthor Index
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