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Vadthiya Narendar

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Journal Articles

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2024
[j5]
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Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad:
A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis. Microelectron. J. 146: 106139 (2024)
2023
[j4]
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Kallepelli Sagar, Satish Maheshwaram, Vadthiya Narendar:
Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes. Microelectron. J. 142: 105986 (2023)
[j3]
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Ravi Kothapally, Vadthiya Narendar, Satish Maheshwaram:
NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications. Microelectron. J. 142: 106018 (2023)
2022
[j2]
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Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad:
On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis. Microelectron. J. 126: 105505 (2022)
2021
[j1]
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  - journals/mj/SreenivasuluN21
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V. Bharath Sreenivasulu, Vadthiya Narendar:
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. Microelectron. J. 116: 105214 (2021)

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