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2010 – 2019
- 2019
[c9]Sayali Patil, Young Bae Kim, Haiqing Nan, Li Li, Ken Choi:
Analysis of Performance Variation of Composite Logic in 7nm CMOS Technology Using SBD Effect Based on TDDB. ISOCC 2019: 237-238- 2015
- [j8]Ken Choi, Haiqing Nan, Wook Choi:
Advances in Smart and Intelligent Multimedia Platforms for Pervasive Computing. Multim. Tools Appl. 74(5): 1537-1539 (2015) - 2014
- [j7]Kyu Won Choi, Haiqing Nan:
Editorial for Special Issue on "Challenges Pervasive Network and Applications for Internet of Things". Mob. Networks Appl. 19(3): 360-362 (2014) - 2013
- [j6]Li Li, Ken Choi, Haiqing Nan:
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration. IEEE Trans. Very Large Scale Integr. Syst. 21(8): 1540-1544 (2013) - 2012
- [j5]Haiqing Nan, Ken Choi:
Low cost and highly reliable hardened latch design for nanoscale CMOS technology. Microelectron. Reliab. 52(6): 1209-1214 (2012) - [j4]Haiqing Nan, Ken Choi:
High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(7): 1445-1457 (2012) - [c8]Haiqing Nan, Ken Choi:
Soft error tolerant latch design with low cost for nanoelectronic systems. ISCAS 2012: 1572-1575 - [c7]Haiqing Nan, Wei Wang, Ken Choi:
Circuit design for carbon nanotube field effect transistors. ISOCC 2012: 351-354 - [c6]Haiqing Nan, Li Li, Ken Choi:
TDDB-based performance variation of combinational logic in deeply scaled CMOS technology. ISQED 2012: 328-333 - 2011
- [j3]Haiqing Nan, Kyung Ki Kim, Wei Wang, Ken Choi:
Dynamic Voltage and Frequency Scaling for Power- Constrained Design using Process Voltage and Temperature Sensor Circuits. J. Inf. Process. Syst. 7(1): 93-102 (2011) - [j2]Haiqing Nan, Ken Choi:
Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology. Microelectron. Reliab. 51(12): 2086-2092 (2011) - [c5]Li Li, Ken Choi, Haiqing Nan:
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously. ISQED 2011: 74-79 - [c4]Sandeep Sriram, Haiqing Nan, Ken Choi:
Low power latch design in near sub-threshold region to improve reliability for soft error. ISQED 2011: 611-614 - 2010
- [c3]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Power gating for ultra-low voltage nanometer ICs. ISCAS 2010: 1472-1475 - [c2]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Adaptive HCI-aware power gating structure. ISQED 2010: 219-224 - [c1]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Hybrid MOSFET/CNFET based power gating structure. SoCC 2010: 334-338
2000 – 2009
- 2009
- [j1]Kyung Ki Kim, Haiqing Nan, Ken Choi:
Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage. IEEE Trans. Circuits Syst. II Express Briefs 56-II(12): 926-930 (2009)
Coauthor Index
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