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ORCIDDaniele Mangano
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2010 – 2019
- 2010
[c6]Daniele Mangano, Giovanni Strano:
Enabling dynamic and programmable QoS in SoCs. NoCArc@MICRO 2010: 17-22
2000 – 2009
- 2008
- [b1]Daniele Mangano:
Advanced architectures for System-on-Chip in deep submicron technologies. University of Pisa, Italy, 2008 - 2007
- [c5]Daniele Mangano, G. Falconeri, Carlo Pistritto, Alberto Scandurra:
Effective full-duplex Mesochronous Link Architecture for Network-on-Chip Data-Link layer. DSD 2007: 519-526 - [c4]Daniele Mangano, Alberto Scandurra, Carlo Pistritto:
Relieving physical issues in new NoC-based SoCs. Nano-Net 2007: 10 - 2006
- [c3]Giuseppe Campobello, Marco Castano, Carmine Ciofi, Daniele Mangano:
GALS networks on chip: a new solution for asynchronous delay-insensitive links. DATE Designers' Forum 2006: 160-165 - [c2]Daniele Mangano, Riccardo Locatelli, Alberto Scandurra, Carlo Pistritto, Marcello Coppola
, Luca Fanucci, Francesco Vitullo, Dario Zandri:
Skew Insensitive Physical Links for Network on Chip. Nano-Net 2006: 1-5 - 2005
- [j1]Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete:
A cache design for high performance embedded systems. J. Embed. Comput. 1(4): 587-597 (2005) - [c1]Pierfrancesco Foglia, Daniele Mangano, Cosimo Antonio Prete:
A NUCA Model for Embedded Systems Cache Design. ESTIMedia 2005: 41-46
Coauthor Index
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