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ORCIDRamayya Kumar
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1990 – 1999
- 1999
[c28]Ramayya Kumar:
Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? VLSI Design 1999- 1998
- [j5]Sofiène Tahar, Ramayya Kumar:
A Practical Methodology for the Formal Verification of RISC Processors. Formal Methods Syst. Des. 13(2): 159-225 (1998) - 1997
- [c27]Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr:
A constructive approach towards correctness of synthesis-application within retiming. ED&TC 1997: 427-431 - 1996
- [c26]Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid:
Formal Synthesis in Circuit Design - A Classification and Survey. FMCAD 1996: 294-309 - [c25]Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar:
Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL. TPHOLs 1996: 157-172 - 1995
- [j4]Sofiène Tahar, Ramayya Kumar:
Formal Specification and Verification Techniques for RISC Pipeline Conflicts. Comput. J. 38(2): 111-120 (1995) - [c24]Dirk Eisenbiegler, Ramayya Kumar:
Formally embedding existing high level synthesis algorithms. CHARME 1995: 71-83 - [c23]Ewa Kwee-Christoph, Fridtjof Feldbusch, Ramayya Kumar, Arno Kunzmann:
Generic design flows for project management in a framework environment. ED&TC 1995: 280-284 - [c22]Dirk Eisenbiegler, Ramayya Kumar:
An Automata Theory Dedicated towards Formal Circuit Synthesis. TPHOLs 1995: 154-169 - [c21]Ramayya Kumar, Thomas Kropf, Klaus Schneider
:
Formal synthesis of circuits with a simple handshake protocol. VLSI Design 1995: 255-259 - 1994
- [j3]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Accelerating Tableaux Proofs Using Compact Representations. Formal Methods Syst. Des. 5(1/2): 145-176 (1994) - [c20]Ramayya Kumar, Sofiène Tahar:
Formal verification of pipeline conflicts in RISC processors. EURO-DAC 1994: 284-289 - [c19]Klaus Schneider, Thomas Kropf, Ramayya Kumar:
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. EDAC-ETC-EUROASIC 1994: 648-652 - [c18]Thomas Kropf, Klaus Schneider, Ramayya Kumar:
A Formal Framework for High Level Synthesis. TPCD 1994: 223-238 - [c17]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Automating Verification by Functional Abstraction at the System Level. TPHOLs 1994: 391-406 - [c16]Sofiène Tahar, Ramayya Kumar:
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. TPHOLs 1994: 424-439 - [e1]Ramayya Kumar, Thomas Kropf:
Theorem Provers in Circuit Design - Theory, Practice and Experience, Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26-28, 1994, Proceedings. Lecture Notes in Computer Science 901, Springer 1994, ISBN 3-540-59047-1 [contents] - 1993
- [j2]Ramayya Kumar, Klaus Schneider, Thomas Kropf:
Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. Formal Methods Syst. Des. 2(2): 165-223 (1993) - [c15]Thomas Kropf, Ramayya Kumar, Klaus Schneider:
Embedding Hardware Verification Within a Commercial Design Framework. CHARME 1993: 242-257 - [c14]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Hardware-Verification using First Order BDDs. CHDL 1993: 45-62 - [c13]Sofiène Tahar, Ramayya Kumar:
Towards a Methodology for the Formal Hierarchical Verification. ICCD 1993: 58-62 - [c12]Dirk Eisenbiegler, Klaus Schneider, Ramayya Kumar:
A Functional Approach for Formalizing Regular Hardware Structures. HUG 1993: 101-114 - [c11]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. HUG 1993: 213-226 - [c10]Sofiène Tahar, Ramayya Kumar:
Implementing a Methodology for Formally Verifying RISC Processors in HOL. HUG 1993: 281-294 - [c9]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. HUG 1993: 385-398 - 1992
- [c8]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
The FAUST - Prover. CADE 1992: 766-770 - [c7]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Efficient Representation and Computation of Tableau Proofs. TPHOLs 1992: 39-57 - [c6]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Modelling Generic Hardware Structures by Abstract Datatypes. TPHOLs 1992: 165-175 - 1991
- [c5]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Automating Most Parts of Hardware Proofs in HOL. CAV 1991: 365-375 - [c4]Fridtjof Feldbusch, Ramayya Kumar:
Verification of synthesized circuits at register transfer level with flow graphs. EURO-DAC 1991: 22-26 - [c3]Ramayya Kumar, Thomas Kropf, Klaus Schneider:
Integrating a First-Order Automatic Prover in the HOL Environment. TPHOLs 1991: 170-176 - [c2]Ramayya Kumar, Thomas Kropf, Klaus Schneider:
First Steps Towards Automating Hardware Proofs in HOL. TPHOLs 1991: 190-193 - [c1]Klaus Schneider, Ramayya Kumar, Thomas Kropf:
Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment. VLSI 1991: 81-90
1980 – 1989
- 1989
- [j1]Thomas Wecker, Ramayya Kumar, Wolfgang Rosenstiel, Heinrich Krämer, Michael Neher:
CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. Inform. Forsch. Entwickl. 4(1): 37-54 (1989)
Coauthor Index
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