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ORCIDYosuke Takahashi
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2020 – today
- 2021
[c7]Hiroki Ikeuchi, Yosuke Takahashi, Kotaro Matsuda, Tsuyoshi Toyono:
Recovery Process Visualization based on Automaton Construction. IM 2021: 10-18
2010 – 2019
- 2018
- [c6]Yosuke Takahashi, Masashi Endo, Hiroaki Matsuno, Hiroaki Muramatsu, Tetsushi Ohki, Masakatsu Nishigaki:
A Study on Human Reflex-Based Biometric Authentication Using Eye-Head Coordination. NBiS 2018: 419-429 - 2016
- [j3]Michihiro Sato, Yosuke Takahashi:
Simulation of Dislocation Accumulation in Impurity Doped-ULSI Cells and Electric Characteristic Evaluations. Int. J. Autom. Technol. 10(2): 195-200 (2016) - 2013
- [c5]Ryo Minegishi, Yosuke Takahashi, Atsushi Takashima, Daisuke Kurabayashi, Ryohei Kanzaki:
Adaptive control system of an insect brain during odor source localization. IROS 2013: 357-362 - [c4]Daisuke Kurabayashi, Yosuke Takahashi, Ryo Minegishi, Elisa Tosello, Enrico Pagello
, Ryohei Kanzaki:
Property Investigation of Chemical Plume Tracing Algorithm in an Insect Using Bio-machine Hybrid System. Living Machines 2013: 131-142 - [c3]Ryo Minegishi, Yosuke Takahashi, Atsushi Takashima, Daisuke Kurabayashi, Ryohei Kanzaki:
Modification in Command Neural Signals of an Insect's Odor Source Searching Behavior on the Brain-Machine Hybrid System. Living Machines 2013: 167-178 - 2010
- [j2]Tomohiko Ogawa, Haruo Kobayashi, Yosuke Takahashi, Nobukazu Takai, Masao Hotta, Hao San, Tatsuji Matsuura, Akira Abe, Katsuyoshi Yagi, Toshihiko Mori:
SAR ADC Algorithm with Redundancy and Digital Error Correction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 415-423 (2010)
2000 – 2009
- 2008
- [j1]Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi:
A Fast Clock Scheduling for Peak Power Reduction in LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3803-3811 (2008) - [c2]Tomohiko Ogawa, Haruo Kobayashi, Masao Hotta, Yosuke Takahashi, Hao San, Nobukazu Takai:
SAR ADC algorithm with redundancy. APCCAS 2008: 268-271 - 2007
- [c1]Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi:
A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI 2007: 582-587
Coauthor Index
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