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Journal Articles
- 2011
[j2]Rashmi Mehrotra, Tom English, Michel P. Schellekens, Steve Hollands, Emanuel M. Popovici:
Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits. J. Low Power Electron. 7(3): 364-380 (2011)- [j1]Tom English, Emanuel M. Popovici, Maurice Keller, William P. Marnane
:
Network-on-Chip interconnect for pairing-based cryptographic IP cores. J. Syst. Archit. 57(1): 95-108 (2011)
Conference and Workshop Papers
- 2012
- [c6]John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers:
A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Hot Interconnects 2012: 9-16 - 2011
- [c5]Tom English, Emanuel M. Popovici:
Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators. NOCS 2011: 225-232 - 2010
- [c4]Rashmi Mehrotra, Tom English, Emanuel M. Popovici, Michel P. Schellekens:
Delay dependent power optimisation of combinational circuits using AND-Inverter graphs. SoCC 2010: 9-14 - 2009
- [c3]Tom English, Ka Lok Man, Emanuel M. Popovici:
BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation. PATMOS 2009: 216-226 - [c2]Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane:
A low-power pairing-based cryptographic accelerator for embedded security applications. SoCC 2009: 369-372 - 2008
- [c1]Tom English, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens:
HotSpot: Visualizing dynamic power consumption in RTL designs. EWDTS 2008: 45-48
Coauthor Index
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