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ORCIDValentin Tihhomirov
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2010 – 2019
- 2016
[j2]Maksim Jenihhin
, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros:
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. 32(3): 273-289 (2016)- [c9]Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar:
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS 2016: 304-309 - 2015
- [c8]N. Palermo, Valentin Tihhomirov, Thiago Santos Copetti, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Marco Gaudesi, Giovanni Squillero, Matteo Sonza Reorda, Fabian Vargas, Letícia Maria Bolzani Pöhls:
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG. LATS 2015: 1-6 - 2014
- [j1]Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Automated Design Error Localization in RTL Designs. IEEE Des. Test 31(1): 83-92 (2014) - [c7]Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar:
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications 2014: 425-436 - 2013
- [c6]Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
Assessment of diagnostic test for automated bug localization. LATW 2013: 1-6 - 2012
- [c5]Maksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov:
PSL assertion checkers synthesis with ASM based HLS tool ABELITE. LATW 2012: 1-6 - [c4]Anton Tsepurov, Valentin Tihhomirov, Maksim Jenihhin, Jaan Raik, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke:
Localization of Bugs in Processor Designs Using zamiaCAD Framework. MTV 2012: 41-47 - [c3]Anton Tsepurov, Gunter Bartsch, Rainer Dorsch, Maksim Jenihhin, Jaan Raik, Valentin Tihhomirov:
A scalable model based RTL framework zamiaCAD for static analysis. VLSI-SoC 2012: 171-176
2000 – 2009
- 2005
- [c2]Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar:
Improved Fault Emulation for Synchronous Sequential Circuits. DSD 2005: 72-78 - 2004
- [c1]Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe:
Evaluating Fault Emulation on FPGA. FPL 2004: 354-363
Coauthor Index
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