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2020 – today
- 2023
[j6]Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta
, Koji Yamazaki, Kimikazu Sano:
High-definition technology of AI inference scheme for object detection on edge/terminal. IEICE Electron. Express 20(13): 20232002 (2023)- [j5]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture. IEICE Trans. Electron. 106(6): 312-320 (2023) - [j4]Daisuke Kobayashi, Ken Nakamura, Masaki Kitahara, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki:
A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming. IEICE Trans. Inf. Syst. 106(1): 46-57 (2023) - 2022
- [c9]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi:
An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture. COOL CHIPS 2022: 1-3 - [c8]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano:
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4 - [c7]Masayuki Sato, Yuya Omori, Ryusuke Egawa, Ken Nakamura, Daisuke Kobayashi, Hiroe Iwasaki, Kazuhiko Komatsu, Hiroaki Kobayashi:
A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders. PDCAT 2022: 288-300 - 2021
- [j3]Hiroyuki Uzawa, Shuhei Yoshida, Yuukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Kimikazu Sano:
High-definition object detection technology based on AI inference scheme and its implementation. IEICE Electron. Express 18(22): 20210323 (2021) - 2020
- [j2]Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. IEICE Trans. Electron. 103-C(3): 77-84 (2020)
2010 – 2019
- 2019
- [c6]Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. COOL CHIPS 2019: 1-3 - [c5]Daisuke Kobayashi, Ken Nakamura, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki:
A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control. GLOBECOM 2019: 1-6 - [c4]Yuya Omori, Ken Nakamura, Takayuki Onishi, Daisuke Kobayashi, Tatsuya Osawa, Hiroe Iwasaki:
4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay. ICECS 2019: 410-413 - [c3]Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki, Atsushi Shimizu:
A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation. ISCAS 2019: 1-5 - [c2]Yuya Omori, Tomotaka Hosotani, Taiichi Otsuji, Katsumi Iwatsuki, Akira Satou:
UTC-PD-Integrated HEMT for Optical-to-Millimeter-Wave Carrier Frequency Down-Conversion. OFC 2019: 1-3 - 2018
- [j1]Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K. IEEE Trans. Multi Scale Comput. Syst. 4(4): 491-499 (2018) - 2017
- [c1]Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu:
A 120 fps high frame rate real-time HEVC video encoder with parallel configuration scalable to 4K. COOL Chips 2017: 1-3
Coauthor Index
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