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ORCIDJeffrey A. Davis
Person information
- affiliation: Georgia Institute of Technology, Atlanta GA, USA
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2020 – today
- 2021
[j12]Pavel V. Kolesnichenko
, Qianhui Zhang, Changxi Zheng, Michael S. Fuhrer, Jeffrey A. Davis:
Multidimensional analysis of excitonic spectra of monolayers of tungsten disulphide: toward computer-aided identification of structural and environmental perturbations of 2D materials. Mach. Learn. Sci. Technol. 2(2): 25021 (2021)
2000 – 2009
- 2008
- [j11]Vinita V. Deodhar, Jeffrey A. Davis:
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(4): 1023-1030 (2008) - 2007
- [j10]Hiroshi Yamamoto, Jeffrey A. Davis:
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 649-659 (2007) - [j9]Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis:
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 990-1002 (2007) - [c18]Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl:
IntSim: A CAD tool for optimization of multilevel interconnect networks. ICCAD 2007: 560-567 - 2006
- [c17]Pranav Anbalagan, Jeffrey A. Davis:
A priori prediction of tightly clustered connections based on heuristic classification trees. SLIP 2006: 9-15 - [c16]Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis:
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. VLSI Design 2006: 773-776 - 2005
- [j8]Vinita V. Deodhar, Jeffrey A. Davis:
Optimization of throughput performance for low-power VLSI interconnects. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 308-318 (2005) - [j7]Ajay Joshi, Jeffrey A. Davis:
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. 13(8): 899-910 (2005) - [c15]Ajay Joshi, Jeffrey A. Davis:
Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. ACM Great Lakes Symposium on VLSI 2005: 446-451 - [c14]Vinita V. Deodhar, Jeffrey A. Davis:
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. ISQED 2005: 592-597 - [c13]Ajay Joshi, Jeffrey A. Davis:
Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing. SoCC 2005: 137-142 - [c12]Vinita V. Deodhar, Jeffrey A. Davis:
Designing for signal integrity in wave-pipelined SOC global interconnects. SoCC 2005: 207-210 - 2004
- [c11]Ajay Joshi, Jeffrey A. Davis:
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). SLIP 2004: 64-68 - [c10]Pranav Anbalagan, Jeffrey A. Davis:
Maximum Multiplicity Distributions for Length Prediction Driven Placement. VLSI Design 2004: 981- - 2003
- [c9]Vinita V. Deodhar, Jeffrey A. Davis:
Voltage scaling and repeater insertion for high-throughput low-power interconnects. ISCAS (5) 2003: 349-352 - [c8]Alex Talpasanu, G. Milford, K. S. A. Miles, Jeffrey A. Davis:
Computer Educational Datapath (CED): Basic Computer Design for K-12 Education. ITCC 2003: 86-90 - [c7]Pranav Anbalagan, Jeffrey A. Davis:
Maximum multiplicity distributions (MMD). SLIP 2003: 107-113 - 2002
- [j6]James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl:
Interconnect opportunities for gigascale integration. IBM J. Res. Dev. 46(2-3): 245-264 (2002) - [c6]Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl:
A physical model for the transient response of capacitively loaded distributed rlc interconnects. DAC 2002: 763-766 - 2001
- [j5]Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). IEEE Trans. Very Large Scale Integr. Syst. 9(6): 899-912 (2001) - [j4]James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Impact of three-dimensional architectures on interconnects in gigascale integration. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 922-928 (2001) - 2000
- [j3]James D. Meindl, Jeffrey A. Davis:
The fundamental limit on binary switching energy for terascale integration (TSI). IEEE J. Solid State Circuits 35(10): 1515-1516 (2000) - [j2]Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 649-659 (2000) - [j1]Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl:
A compact physical via blockage model. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 689-692 (2000) - [c5]Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl:
Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. ISLPED 2000: 167-172 - [c4]Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl:
Prediction of interconnect fan-out distribution using Rent's rule. SLIP 2000: 107-112 - [c3]James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl:
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. SLIP 2000: 123-127 - [c2]Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl:
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). SLIP 2000: 147-148
1990 – 1999
- 1998
- [c1]Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl:
On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule. CICC 1998: 93-96
Coauthor Index
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