"Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for ..."

Vinita V. Deodhar, Jeffrey A. Davis (2005)

> Home

Details and statistics

DOI: 10.1109/ISQED.2005.128

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/isqed/DeodharD05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/isqed/DeodharD05
Vinita V. Deodhar, Jeffrey A. Davis:
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. ISQED 2005: 592-597

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.