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2020 – today
- 2024
[c26]Chia-Yu Chou, Tzu-Yi Hung, Tsung-Chu Huang:
SievingNet: Ternary-Coded Binary Based Approximate Sieving for Neural Network. ICCE-Taiwan 2024: 9-10- [c25]Yu-Liang Chen, Ren-Xiang Liu, Tsung-Chu Huang:
Flosit: Float/Posit Coarchitecture Exploiting Value Location in Neural Network. ICCE-Taiwan 2024: 11-12 - 2023
- [c24]Ting-Yu Chen, Zong-Yu Wang, Tsung-Chu Huang:
TCB Convolution: Ternary-Coded Binarized Convolutions with Fixed-Point Filters. ICCE-Taiwan 2023: 95-96 - [c23]Che Lin, Heng Hsu, Tsung-Chu Huang:
Redundant Lagrange Interpolation for Fault-Tolerant Winograd Convolution. ICCE-Taiwan 2023: 97-98 - 2022
- [c22]Wan Ju Huang, Hsiao-Wen Fu, Tsung-Chu Huang:
AN-HRNS: AN-Coded Hierarchical Residue Number System for Reliable Neural Network Accelerators. ATS 2022: 132-137 - [c21]Jyun-Xin Ke, Siang-En Ciou, Ting-Yu Chen, Tsung-Chu Huang:
SPINDLE: Self-Pretrainable In-situ Normalizer for Deep Learning Error Function. ICCE-TW 2022: 59-60 - [c20]Kuan-Yu Huang, Jettae Schroff, Cheng-Di Tsai, Tsung-Chu Huang:
2DAN-BNN: Two-Dimensional AN-Code Decoders for Binarized Neural Networks. ICCE-TW 2022: 147-148 - 2021
- [c19]Cheng-Di Tsai, Ting-Yu Chen, Hsiao-Wen Fu, Tsung-Chu Huang:
TCBNN: Error-Correctable Ternary-Coded Binarized Neural Network. AICAS 2021: 1-4 - [c18]Ting-Yu Chen, Cheng-Di Tsai, Hsiao-Wen Fu, Yung-Chun Yang, Tsung-Chu Huang:
Error Correctable Range-Addressable Lookup for Activation and Quantization in AI Automotive Electronics. ICCE-TW 2021: 1-2 - [c17]Hsiao-Wen Fu, Ting-Yu Chen, Cheng-Di Tsai, Meng-Wei Shen, Tsung-Chu Huang:
AN-Coded Redundant Residue Number System for Reliable Neural Networks. ICCE-TW 2021: 1-2 - [c16]Cho-Sheng Lin, Jing Huang, Po-Sheng Chang, Chun-Yen Tsai, Tsung-Chu Huang:
SAFER & SAFEST: Single-Aging-Factor Enhanced Rings and Shadow Trees for Data Annotation and Early Warning in Online Aging Monitors of Automotive SoCs. ICCE-TW 2021: 1-2 - [c15]Cheng-Di Tsai, Hsiao-Wen Fu, Ting-Yu Chen, Tsung-Chu Huang:
TAIWAN Online: Test AI with AN Codes Online for Automotive Chips. ITC-Asia 2021: 1-6 - 2020
- [c14]Liang-Yu Lin, Jerrae Schroff, Tsu-Ping Lin, Tsung-Chu Huang:
Residue Number System Design Automation for Neural Network Acceleration. ICCE-TW 2020: 1-2 - [c13]Liang-Yu Lin, Jerrae Schroff, Chia-Cheng Liang, Tsung-Chu Huang:
Approximate Computing for Batch Learning in Neural Network. ICCE-TW 2020: 1-2 - [c12]Wen-Chang Yang, Shu-Yun Lin, Tsung-Chu Huang:
Range-Lookup Approximate Computing Acceleration for Any Activation Functions in Low-Power Neural Network. ICCE-TW 2020: 1-2
2010 – 2019
- 2019
- [c11]Tsung-Chu Huang:
Self-Checking Residue Number System for Low-Power Reliable Neural Network. ATS 2019: 37-42 - [c10]Tsung-Chu Huang, Chun-Hao Chiang, Mo-Han Lin:
Low-Cost and Fast Design of Precise Activation Functions in Neural Network. ICCE-TW 2019: 1-2 - 2018
- [c9]Tsung-Chu Huang, Jeffae Schroff:
Precompensation, BIST and Analogue Berger Codes for Self-Healing of Neuromorphic RRAM. ATS 2018: 173-178 - 2015
- [j7]Tsung-Chu Huang:
Cluster Error Correction for Real-Time Channels by Unbound Rotation of Two-Dimensional Parity-Check Codes. IEEE Commun. Lett. 19(6): 917-920 (2015) - 2011
- [j6]Tsung-Chu Huang:
High-yield performance-efficient redundancy analysis for 2D memory. Sci. China Inf. Sci. 54(8): 1663-1676 (2011) - 2010
- [c8]Tsung-Chu Huang, Kuei-Yeh Lu, Yen-Chieh Huang:
HYPERA: High-Yield Performance-Efficient Redundancy Analysis. Asian Test Symposium 2010: 231-236
2000 – 2009
- 2009
- [j5]Tsung-Chu Huang:
Multi-valued equal-weight codes for self-checking and matching. IEEE Commun. Lett. 13(12): 947-949 (2009) - 2008
- [j4]Tsung-Chu Huang:
A Low-Power Dependable Berger Code for Fully Asymmetric Communication. IEEE Commun. Lett. 12(10): 773-775 (2008) - 2007
- [c7]Tsung-Chu Huang, Gau-Bin Chang, Ling Li:
Congruence Synchronous Mirror Delay. ISCAS 2007: 2184-2187 - 2002
- [j3]Kuen-Jong Lee, Tsung-Chu Huang:
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application. J. Electron. Test. 18(6): 627-636 (2002) - 2001
- [j2]Tsung-Chu Huang, Kuen-Jong Lee:
Reduction of power consumption in scan-based circuits during testapplication by an input control technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(7): 911-917 (2001) - [c6]Tsung-Chu Huang, Kuen-Jong Lee:
A Low-Power LFSR Architecture. Asian Test Symposium 2001: 470 - [c5]Tsung-Chu Huang, Kuen-Jong Lee:
A token scan architecture for low power testing. ITC 2001: 660-669 - 2000
- [c4]Kuen-Jong Lee, Tsung-Chu Huang, Jih-Jeen Chen:
Peak-power reduction for multiple-scan circuits during test application. Asian Test Symposium 2000: 453-458
1990 – 1999
- 1999
- [j1]Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang:
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. ACM Trans. Design Autom. Electr. Syst. 4(2): 194-218 (1999) - [c3]Tsung-Chu Huang, Kuen-Jong Lee:
An Input Control Technique for Power Reduction in Scan Circuits During Test Application. Asian Test Symposium 1999: 315-320 - 1997
- [c2]Tsung-Chu Huang, Min-Cheng Huang, Kuen-Jong Lee:
Built-in current sensor designs based on the bulk-driven technique. Asian Test Symposium 1997: 384- - 1996
- [c1]Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai:
Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. Asian Test Symposium 1996: 100-
Coauthor Index
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