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ORCIDEleonora Schönborn
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2010 – 2019
- 2016
[b1]Eleonora Schönborn:
Scalable Design and Synthesis of Reversible Circuits. University of Bremen, Germany, 2016- [j1]Robert Wille
, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler:
SyReC: A hardware description language for the specification and synthesis of reversible circuits. Integr. 53: 39-53 (2016) - 2015
- [c7]Eleonora Schönborn, Rolf Drechsler:
Design and Synthesis of Reversible Circuits using Hardware Description Languages. SyDe Summer School 2015: 296-298 - [c6]Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. VLSID 2015: 435-440 - 2014
- [c5]Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
Optimizing DD-based synthesis of reversible circuits using negative control lines. DDECS 2014: 129-134 - [c4]Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler:
RevVis: Visualization of Structures and Properties in Reversible Circuits. RC 2014: 111-124 - 2012
- [c3]Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler:
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI 2012: 213-218 - 2011
- [c2]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler:
Designing a RISC CPU in Reversible Logic. ISMVL 2011: 170-175 - [c1]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler:
Designing a RISC CPU in Reversible Logic. MBMV 2011: 249-258
Coauthor Index
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