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Journal Articles
- 2024
[j4]Wei Tang
, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Rani Kale, Mark Flanigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. IEEE J. Solid State Circuits 59(4): 1235-1245 (2024)- 2021
- [j3]Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang:
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. IEEE J. Solid State Circuits 56(2): 612-623 (2021) - 2018
- [j2]Chester Liu, Sung-Gun Cho, Zhengya Zhang:
A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. IEEE J. Solid State Circuits 53(10): 2818-2827 (2018) - 2014
- [j1]Sung-Gun Cho, Daesung Kim, Jinho Choi, Jeongseok Ha:
Block-Wise Concatenated BCH Codes for NAND Flash Memories. IEEE Trans. Commun. 62(4): 1164-1177 (2014)
Conference and Workshop Papers
- 2023
- [c8]Wei Tang, Sung-Gun Cho, Tim Tri Hoang, Jacob Botimer, Wei Qiang Zhu, Ching-Chi Chang, Cheng-Hsun Lu, Junkang Zhu, Yaoyu Tao, Tianyu Wei, Naomi Kavi Motwani, Mani Yalamanchi, Ramya Yarlagadda, Sirisha Kale, Mark Flannigan, Allen Chan, Thungoc Tran, Sergey Y. Shumarayev, Zhengya Zhang:
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. VLSI Technology and Circuits 2023: 1-2 - 2021
- [c7]Sung-Gun Cho, Wei Tang, Chester Liu, Zhengya Zhang:
PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. VLSI Circuits 2021: 1-2 - 2019
- [c6]Sung-Gun Cho, Edith Beigné, Zhengya Zhang:
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. CICC 2019: 1-4 - [c5]Yaoyu Tao, Sung-Gun Cho, Zhengya Zhang:
A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. VLSI Circuits 2019: 240- - 2017
- [c4]Chester Liu, Sung-Gun Cho, Zhengya Zhang:
A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. A-SSCC 2017: 233-236 - [c3]Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang:
Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes. GLOBECOM 2017: 1-6 - 2016
- [c2]Shuanghong Sun, Sung-Gun Cho, Zhengya Zhang:
Error patterns in belief propagation decoding of polar codes and their mitigation methods. ACSSC 2016: 1199-1203 - 2012
- [c1]Sung-Gun Cho, Jeongseok Ha:
Concatenated BCH codes for NAND flash memories. ICC 2012: 2611-2616
Coauthor Index
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