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2010 – 2019
- 2019
[j3]Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang:
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Sustain. Comput. Informatics Syst. 22: 206-218 (2019)- 2018
- [j2]Yuanhui Ni, Weiwen Chen, Lei Wang, Keni Qiu:
面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM). 计算机科学 45(6A): 562-567 (2018) - [c5]Yuanhui Ni, Weiwen Chen, Wenjuan Cui, Yuanchun Zhou, Keni Qiu:
Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN. DATE 2018: 1183-1186 - [c4]Yuanhui Ni, Keni Qiu, Weiwen Chen, Lixue Xia, Yu Wang:
Low power driven loop tiling for RRAM crossbar-based CNN. SAC 2018: 375-380 - 2017
- [j1]Yuanhui Ni
, Zhiyao Gong, Weiwen Chen, Chengmo Yang, Keni Qiu:
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. VLSI Design 2017: 1030249:1-1030249:9 (2017) - [c3]Weiwen Chen, Keni Qiu, Jiqin Zhou, Yuanhui Ni, Yuanchao Xu:
Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus. TrustCom/BigDataSE/ICESS 2017: 839-843 - [c2]Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang:
Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. TrustCom/BigDataSE/ICESS 2017: 844-852 - 2016
- [c1]Keni Qiu, Yuanhui Ni, Weigong Zhang, Jing Wang, Xiaoqiang Wu, Chun Jason Xue, Tao Li:
An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor. ICCD 2016: 9-16
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