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ORCIDAmir Roth
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Journal Articles
- 2010
[j10]Andrew D. Hilton, Amir Roth:
SMT-Directory: Efficient Load-Load Ordering for SMT. IEEE Comput. Archit. Lett. 9(1): 25-28 (2010)- [j9]Andrew D. Hilton, Santosh Nagarakatte
, Amir Roth:
iCFP: Tolerating All-Level Cache Misses in In-Order Processors. IEEE Micro 30(1): 12-19 (2010) - 2008
- [j8]Amir Roth:
Physical Register Reference Counting. IEEE Comput. Archit. Lett. 7(1): 9-12 (2008) - 2007
- [j7]Tingting Sha, Milo M. K. Martin, Amir Roth:
NoSQ: Store-Load Communication without a Store Queue. IEEE Micro 27(1): 106-113 (2007) - 2006
- [j6]Amir Roth:
Store Vulnerability Window (SVW): A Filter and Potential Replacement for Load Re-Execution. J. Instr. Level Parallelism 8 (2006) - 2005
- [j5]Marc L. Corliss, E. Christopher Lewis, Amir Roth:
Using DISE to protect return addresses from attack. SIGARCH Comput. Archit. News 33(1): 65-72 (2005) - [j4]Marc L. Corliss, E. Christopher Lewis, Amir Roth:
The implementation and evaluation of dynamic code decompression using DISE. ACM Trans. Embed. Comput. Syst. 4(1): 38-72 (2005) - 2001
- [j3]Gurindar S. Sohi, Amir Roth:
Speculative Multithreaded Processors. Computer 34(4): 66-71 (2001) - [j2]Amir Roth, Gurindar S. Sohi:
Squash Reuse via a Simplified Implementation of Register Integration. J. Instr. Level Parallelism 3 (2001) - [j1]Amir Roth, Ronny Ronen, Avi Mendelson:
Dynamic techniques for load and load-use scheduling. Proc. IEEE 89(11): 1621-1637 (2001)
Conference and Workshop Papers
- 2012
- [c25]Amir Roth:
Near term computing opportunities in building energy efficiency. IGCC 2012: 1-5 - [c24]Steven J. Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth:
Flexible register management using reference counting. HPCA 2012: 273-284 - 2010
- [c23]Andrew D. Hilton, Amir Roth:
BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution. HPCA 2010: 1-12 - 2009
- [c22]Andrew D. Hilton, Neeraj Eswaran, Amir Roth:
CPROB: Checkpoint Processing with Opportunistic Minimal Recovery. PACT 2009: 159-168 - [c21]Andrew D. Hilton, Santosh Nagarakatte, Amir Roth:
iCFP: Tolerating all-level cache misses in in-order processors. HPCA 2009: 431-442 - [c20]Andrew D. Hilton, Amir Roth:
Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors. ISCA 2009: 245-254 - 2007
- [c19]Andrew D. Hilton, Amir Roth:
Ginger: control independence using tag rewriting. ISCA 2007: 436-447 - 2006
- [c18]Anne Bracy, Amir Roth:
Serialization-Aware Mini-Graphs: Performance with Fewer Resources. MICRO 2006: 171-184 - [c17]Tingting Sha, Milo M. K. Martin, Amir Roth:
NoSQ: Store-Load Communication without a Store Queue. MICRO 2006: 285-296 - 2005
- [c16]Marc L. Corliss, E. Christopher Lewis, Amir Roth:
Low-Overhead Interactive Debugging via Dynamic Instrumentation with DISE. HPCA 2005: 303-314 - [c15]Vlad Petric, Tingting Sha, Amir Roth:
RENO - A Rename-Based Instruction Optimizer. ISCA 2005: 98-109 - [c14]Vlad Petric, Amir Roth:
Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection. ISCA 2005: 322-333 - [c13]Amir Roth:
Store Vulnerability Window (SVW): Re-Execution Filtering for Enhanced Load Optimization. ISCA 2005: 458-468 - [c12]Tingting Sha, Milo M. K. Martin, Amir Roth:
Scalable Store-Load Forwarding via Store Queue Index Prediction. MICRO 2005: 159-170 - 2004
- [c11]Anne Bracy, Prashant Prahlad, Amir Roth:
Dataflow Mini-Graphs: Amplifying Superscalar Capacity and Bandwidth. MICRO 2004: 18-29 - 2003
- [c10]Marc L. Corliss, E. Christopher Lewis, Amir Roth:
DISE: A Programmable Macro Engine for Customizing Applications. ISCA 2003: 362-373 - [c9]Marc L. Corliss, E. Christopher Lewis, Amir Roth:
A DISE implementation of dynamic code decompression. LCTES 2003: 232-243 - 2002
- [c8]Vlad Petric, Anne Bracy, Amir Roth:
Three extensions to register integration. MICRO 2002: 37-47 - [c7]Amir Roth, Gurindar S. Sohi:
A quantitative framework for automated pre-execution thread selection. MICRO 2002: 430-441 - 2001
- [c6]Amir Roth, Gurindar S. Sohi:
Speculative Data-Driven Multithreading. HPCA 2001: 37-48 - 2000
- [c5]Amir Roth, Gurindar S. Sohi:
Register integration: a simple and efficient implementation of squash reuse. MICRO 2000: 223-234 - 1999
- [c4]Amir Roth, Andreas Moshovos, Gurindar S. Sohi:
Improving virtual function call target prediction via dependence-based pre-computation. International Conference on Supercomputing 1999: 356-364 - [c3]Amir Roth, Gurindar S. Sohi:
Effective Jump-Pointer Prefetching for Linked Data Structures. ISCA 1999: 111-121 - 1998
- [c2]Amir Roth, Andreas Moshovos, Gurindar S. Sohi:
Dependance Based Prefetching for Linked Data Structures. ASPLOS 1998: 115-126 - 1997
- [c1]Milo M. K. Martin, Amir Roth, Charles N. Fischer:
Exploiting Dead Value Information. MICRO 1997: 125-135
Coauthor Index
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