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ORCIDRyutaro Doi
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2020 – today
- 2020
[j4]Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto
:
A Fault Detection and Diagnosis Method for Via-Switch Crossbar in Non-Volatile FPGA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1447-1455 (2020)- [j3]Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto:
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 2572-2587 (2020) - [c6]Ryutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto:
Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGA. DATE 2020: 983-986 - [c5]Masanori Hashimoto, Xu Bai, Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto, Jaehoon Yu, Ryutaro Doi, Yusuke Araki, Hidetoshi Onodera, Takashi Imagawa, Hiroyuki Ochi, Kazutoshi Wakabayashi, Yukio Mitsuyama, Tadahiko Sugibayashi:
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. ISSCC 2020: 502-504
2010 – 2019
- 2018
- [j2]Ryutaro Doi, Masanori Hashimoto, Takao Onoye:
An analytic evaluation on soft error immunity enhancement due to temporal triplication. Int. J. Embed. Syst. 10(1): 22-31 (2018) - [j1]Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto:
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2723-2736 (2018) - [c4]Ryutaro Doi, Jaehoon Yu, Masanori Hashimoto:
Sneak path free reconfiguration of via-switch crossbars based FPGA. ICCAD 2018: 68 - [c3]Ryutaro Doi, Masanori Hashimoto:
SAT Encoding-Based Verification of Sneak Path Problem in Via-Switch FPGA. ISVLSI 2018: 429-434 - [c2]Masanori Hashimoto, Yuki Nakazawa, Ryutaro Doi, Jaehoon Yu:
Interconnect Delay Analysis for RRAM Crossbar Based FPGA. ISVLSI 2018: 522-527 - 2016
- [c1]Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. FPL 2016: 1-4
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