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ORCIDWerner Geurts
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2010 – 2019
- 2015
[j5]Roberto Ammendola
, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces. Future Gener. Comput. Syst. 53: 109-118 (2015)- 2013
- [i1]Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini:
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report. CoRR abs/1307.1270 (2013)
2000 – 2009
- 2006
- [c10]Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet:
Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite. SoC 2006: 1-4 - 2001
- [j4]Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens:
Processor modeling and code selection for retargetable compilation. ACM Trans. Design Autom. Electr. Syst. 6(3): 277-307 (2001) - [c9]Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man:
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. ACM Great Lakes Symposium on VLSI 2001: 19-24
1990 – 1999
- 1997
- [j3]Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts, Augusli Kifli, Clifford Liem, Pierre G. Paulin:
Embedded software in real-time signal processing systems: design technologies. Proc. IEEE 85(3): 436-454 (1997) - 1996
- [c8]Johan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man:
A Graph Based Processor Model for Retargetable Code Generation. ED&TC 1996: 102-107 - 1995
- [j2]Werner Geurts, Francky Catthoor, Hugo De Man:
Quadratic zero-one programming-based synthesis of application-specific data paths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 1-11 (1995) - 1994
- [c7]Francky Catthoor, Werner Geurts, Hugo De Man:
Loop transformation methodology for fixed-rate video, image and telecom processing applications. ASAP 1994: 427-438 - [c6]Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens:
Chess: retargetable code generation for embedded DSP processors. Code Generation for Embedded Processors 1994: 85-102 - [c5]Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man:
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. EDAC-ETC-EUROASIC 1994: 490-494 - 1993
- [j1]Johannes Steensma, Werner Geurts, Francky Catthoor, Hugo De Man:
Testability analysis in high level data path synthesis. J. Electron. Test. 4(1): 43-56 (1993) - [c4]Werner Geurts, Francky Catthoor, Hugo De Man:
Quadratic zero-one programming based synthesis of application specific data paths. ICCAD 1993: 522-525 - 1992
- [c3]Werner Geurts, Francky Catthoor, Hugo De Man:
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing. DAC 1992: 124-127 - 1991
- [c2]Stefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man:
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications. DAC 1991: 597-602 - [c1]Werner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man:
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. VLSI 1991: 193-202
Coauthor Index
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