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Journal Articles
- 2019
[j2]Thomas Polzer, Florian Huemer
, Andreas Steininger:
An Experimental Study of Metastability-Induced Glitching Behavior. J. Circuits Syst. Comput. 28(Supplement-1): 1940006:1-1940006:21 (2019)- 2018
- [j1]Thomas Polzer, Florian Huemer, Andreas Steininger:
Refined metastability characterization using a time-to-digital converter. Microelectron. Reliab. 80: 91-99 (2018)
Conference and Workshop Papers
- 2024
- [c14]Florian Huemer:
QDI Binary Comparator Networks and their Application in Combinational Logic. DDECS 2024: 92-97 - [c13]Florian Huemer, David Leopoldseder, Aleksandar Prokopec, Raphael Mosaner, Hanspeter Mössenböck:
Taking a Closer Look: An Outlier-Driven Approach to Compilation-Time Optimization. ECOOP 2024: 20:1-20:28 - 2023
- [c12]Zaheer Tabassam, Andreas Steininger, Robert Najvirt, Florian Huemer:
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. ASYNC 2023: 48-57 - 2022
- [c11]Florian Huemer, Robert Najvirt, Andreas Steininger:
On SAT-Based Model Checking of Speed-Independent Circuits. DDECS 2022: 100-105 - 2021
- [c10]Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger, Zaheer Tabassam:
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. ASYNC 2021: 25-33 - [c9]Patrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger:
An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. DSD 2021: 541-548 - 2020
- [c8]Florian Huemer, Andreas Steininger:
Timing Domain Crossing using Muller Pipelines. ASYNC 2020: 44-53 - 2018
- [c7]Florian Huemer, Andreas Steininger:
Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication. ASYNC 2018: 17-25 - [c6]Florian Huemer, Thomas Polzer, Andreas Steininger:
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. DDECS 2018: 141-146 - [c5]Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner:
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. DFT 2018: 1-6 - 2017
- [c4]Thomas Polzer, Florian Huemer, Andreas Steininger:
Measuring metastability using a time-to-digital converter. DDECS 2017: 116-121 - 2016
- [c3]Florian Huemer, Jakob Lechner, Andreas Steininger:
A new coding scheme for fault tolerant 4-phase delay-insensitive codes. ICCD 2016: 392-395 - [c2]Attila Kinali, Florian Huemer, Christoph Lenzen:
Fault-Tolerant Clock Synchronization with High Precision. ISVLSI 2016: 490-495 - 2015
- [c1]Jakob Lechner, Andreas Steininger, Florian Huemer:
Methods for analysing and improving the fault resilience of delay-insensitive codes. ICCD 2015: 519-526
Coauthor Index
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