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ORCIDReza Hojabr
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2020 – today
- 2022
[c11]Parmida Vahdatniya, Amirali Sharifian, Reza Hojabr, Arrvindh Shriraman:
mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL. PACT 2022: 346-358- [c10]Ali Sedaghati, Milad Hakimi, Reza Hojabr, Arrvindh Shriraman:
X-cache: a modular architecture for domain-specific caches. ISCA 2022: 396-409 - 2021
- [j3]Kamyar Givaki
, Reza Hojabr, MohammadHosein Gholamrezaei, Ahmad Khonsari, Saeid Gorgin, Dara Rahmati, M. Hassan Najafi:
High-Performance Deterministic Stochastic Computing Using Residue Number System. IEEE Des. Test 38(6): 60-68 (2021) - [c9]Naveen Vedula, Reza Hojabr, Ahmad Khonsari, Arrvindh Shriraman:
X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions. PACT 2021: 103-115 - [c8]Reza Hojabr, Ali Sedaghati, Amirali Sharifian, Ahmad Khonsari, Arrvindh Shriraman:
SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs. HPCA 2021: 84-96 - [c7]Minh Bui, Michael Lu, Reza Hojabr, Mo Chen, Arrvindh Shriraman:
Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA. IROS 2021: 1666-1673 - 2020
- [c6]Reza Hojabr, Kamyar Givaki, Kossar Pourahmadi, Parsa Nooralinejad, Ahmad Khonsari, Dara Rahmati, M. Hassan Najafi:
TaxoNN: A Light-Weight Accelerator for Deep Neural Network Training. ISCAS 2020: 1-5 - [c5]Kamyar Givaki, Behzad Salami, Reza Hojabr, S. M. Reza Tayaranian, Ahmad Khonsari, Dara Rahmati, Saeid Gorgin, Adrián Cristal, Osman S. Unsal:
On the Resilience of Deep Learning for Reduced-voltage FPGAs. PDP 2020: 110-117 - [i3]Kamyar Givaki, Behzad Salami, Reza Hojabr, S. M. Reza Tayaranian, Ahmad Khonsari, Dara Rahmati, Saeid Gorgin, Adrián Cristal, Osman S. Unsal:
On the Resilience of Deep Learning for Reduced-voltage FPGAs. CoRR abs/2001.00053 (2020) - [i2]Reza Hojabr, Kamyar Givaki, Kossar Pourahmadi, Parsa Nooralinejad, Ahmad Khonsari, Dara Rahmati, M. Hassan Najafi:
TaxoNN: A Light-Weight Accelerator for Deep Neural Network Training. CoRR abs/2010.05197 (2020) - [i1]Minh Bui, Michael Lu, Reza Hojabr, Mo Chen, Arrvindh Shriraman:
Real-Time Formal Verification of Autonomous Systems With An FPGA. CoRR abs/2012.04011 (2020)
2010 – 2019
- 2019
- [c4]Kamyar Givaki, Reza Hojabr, M. Hassan Najafi, Ahmad Khonsari, M. Hossein Gholamrezayi, Saeid Gorgin, Dara Rahmati:
Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication. ASAP 2019: 40 - [c3]Reza Hojabr, Kamyar Givaki, S. M. Reza Tayaranian, Parsa Esfahanian, Ahmad Khonsari, Dara Rahmati, M. Hassan Najafi:
SkippyNN: An Embedded Stochastic-Computing Accelerator for Convolutional Neural Networks. DAC 2019: 132 - [c2]Amirali Sharifian, Reza Hojabr, Navid Rahimi, Sihao Liu, Apala Guha, Tony Nowatzki, Arrvindh Shriraman:
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators. MICRO 2019: 940-953 - 2017
- [j2]Ali Yasoubi, Reza Hojabr, Mehdi Modarressi:
Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse. IEEE Comput. Archit. Lett. 16(1): 72-75 (2017) - [j1]Reza Hojabr, Mehdi Modarressi, Masoud Daneshtalab, Ali Yasoubi, Ahmad Khonsari:
Customizing Clos Network-on-Chip for Neural Networks. IEEE Trans. Computers 66(11): 1865-1877 (2017) - 2015
- [c1]Ali Yasoubi, Reza Hojabr, Hengameh Takshi, Mehdi Modarressi, Masoud Daneshtalab:
CuPAN - High Throughput On-chip Interconnection for Neural Networks. ICONIP (3) 2015: 559-566
Coauthor Index
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