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ORCIDManash Chanda
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2020 – today
- 2023
[j9]Adrija Mukherjee, Papiya Debnath, D. Nirmal, Manash Chanda:
A new analytical modelling of 10 nm negative capacitance-double gate TFET with improved cross talk and miller effects in digital circuit applications. Microelectron. J. 133: 105689 (2023)- 2022
- [j8]Gargi Jana, Dipanjan Sen, Papiya Debnath
, Manash Chanda:
Power and delay analysis of dielectric modulated dual cavity Junctionless double gate field effect transistor based label-free biosensor. Comput. Electr. Eng. 99: 107828 (2022) - [j7]Tanushree Ganguli, Manash Chanda, Angsuman Sarkar:
Impact of Interface Trap Charges on the Performances of Junctionless MOSFET in Sub-Threshold Regime. Comput. Electr. Eng. 100: 107914 (2022) - 2021
- [j6]Shreya Bhattacharyya, Souvik Majumder, Papiya Debnath, Manash Chanda:
Arrhythmic Heartbeat Classification Using Ensemble of Random Forest and Support Vector Machine Algorithm. IEEE Trans. Artif. Intell. 2(3): 260-268 (2021) - 2020
- [j5]Avtar Singh, Saurabh Chaudhury, Manash Chanda, Chandan Kumar Sarkar:
Split gated silicon nanotube FET for bio-sensing applications. IET Circuits Devices Syst. 14(8): 1289-1294 (2020)
2010 – 2019
- 2018
- [j4]Manash Chanda, Sandipta Mal, Akash Mondal, Chandan Kumar Sarkar:
Design and analysis of a logic model for ultra-low power near threshold adiabatic computing. IET Circuits Devices Syst. 12(4): 439-446 (2018) - 2017
- [j3]Manash Chanda, Tanushree Ganguli, Sandipta Mal, Anindita Podder, Chandan Kumar Sarkar:
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application. J. Low Power Electron. 13(3): 472-481 (2017) - 2015
- [j2]Manash Chanda, Swapnadip De, Chandan Kumar Sarkar:
Design and Analysis of 32-Bit CLA Using Energy Efficient Adiabatic Logic for Ultra-Low-Power Application. J. Circuits Syst. Comput. 24(10): 1550160:1-1550160:20 (2015) - [j1]Manash Chanda, Sankalp Jain, Swapnadip De, Chandan Kumar Sarkar:
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2782-2790 (2015) - 2014
- [c1]Manash Chanda, Ananda Sankar Chakraborty, S. Nag, Raina Modak:
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application. VDAT 2014: 1-2
Coauthor Index
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