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ORCIDRenato Fernandes Hentschke
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2010 – 2019
- 2019
[c18]Gyuszi Suto, Geoff S. Greenleaf, Phanindra Bhagavatula, Heinrich R. Fischer, Sanjay K. Soni, Brian H. Miller, Renato Fernandes Hentschke:
Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling. ISPD 2019: 75-82- 2014
- [j5]Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Algorithms for Maze Routing With Exact Matching Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 101-112 (2014) - 2012
- [j4]Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias. RITA 19(1): 28-45 (2012) - [c17]Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Maze routing algorithms with exact matching constraints for analog and mixed signal designs. ICCAD 2012: 130-136 - 2011
- [j3]Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
An Algorithmic Study of Exact Route Matching for Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1842-1855 (2011)
2000 – 2009
- 2009
- [j2]Renato Fernandes Hentschke, Jagannathan Narasimhan, Marcelo O. Johann, Ricardo Reis:
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff. IEEE Trans. Very Large Scale Integr. Syst. 17(8): 1073-1086 (2009) - [c16]Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
Exact route matching algorithms for analog and mixed signal integrated circuits. ICCAD 2009: 231-238 - 2007
- [c15]Renato Fernandes Hentschke, Ricardo Reis:
A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length. ISCAS 2007: 2036-2039 - [c14]Renato Fernandes Hentschke, Jaganathan Narasimham, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
Maze routing steiner trees with effective critical sink optimization. ISPD 2007: 135-142 - [c13]Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
3D-Vias Aware Quadratic Placement for 3D VLSI Circuits. ISVLSI 2007: 67-72 - [c12]Guilherme Flach, Marcelo O. Johann, Renato Fernandes Hentschke, Ricardo Reis:
Cell placement on graphics processing units. SBCCI 2007: 87-92 - 2006
- [c11]Sandro Sawicki
, Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits. ICECS 2006: 399-402 - [c10]Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. SBCCI 2006: 220-225 - [c9]Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Augusto da Luz Reis:
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias. VLSI-SoC 2006: 128-133 - [c8]Renato Fernandes Hentschke, Sandro Sawicki, Marcelo O. Johann, Ricardo Reis:
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits. VLSI-SoC (Selected Papers) 2006: 259-279 - 2005
- [c7]Renato Fernandes Hentschke, Marcelo O. Johann, Ricardo Reis:
Blue Macaw: A Didactic Placement Tool Using Simulated Annealing. EDUTECH 2005: 37-47 - [c6]Renato Fernandes Hentschke, Jagannathan Narasimhan, David S. Kung:
Improving run times by pruned application of synthesis transforms. SBCCI 2005: 38-43 - 2004
- [j1]Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis:
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. IEEE Des. Test Comput. 21(6): 552-562 (2004) - [c5]Júlio C. B. de Mattos, Lisane B. de Brisolara, Renato Fernandes Hentschke, Luigi Carro, Flávio Rech Wagner:
Design Space Exploration with Automatic Generation of IP-Based Embedded Software. DIPES 2004: 237-246 - 2003
- [c4]Renato Fernandes Hentschke, Ricardo Reis:
Plic-Plac: a novel constructive algorithm for placement. ISCAS (5) 2003: 461-464 - [c3]Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis:
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. SBCCI 2003: 267- - [c2]Renato Fernandes Hentschke, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
A study on the performance of fast initial placement algorithms. VLSI-SOC 2003: 204- - 2002
- [c1]Renato Fernandes Hentschke, Felipe S. Marques, Fernanda Lima, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis:
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy. SBCCI 2002: 95-100
Coauthor Index
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