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ORCIDVikas Mahor
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2010 – 2019
- 2019
[c7]Vikas Mahor, Srishti Agrawal, Rekha Gupta:
Image Filtering with Iterative Wavelet Transform Based Compression. ICACDS (2) 2019: 250-262- 2018
- [j4]Vikas Mahor, Manisha Pattanaik:
A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design. Circuits Syst. Signal Process. 37(2): 475-499 (2018) - [c6]Shubhranil Kundu, Vikas Mahor, Rekha Gupta:
A Highly Accurate Fire Detection Method Using Discriminate Method. ICACCI 2018: 1184-1189 - 2017
- [j3]Vikas Mahor, Manisha Pattanaik:
An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File. Circuits Syst. Signal Process. 36(12): 4789-4808 (2017) - 2016
- [c5]Vivek Kumar, Vikas Mahor, Manisha Pattanaik:
Novel Ultra Low Leakage FinFET Based SRAM Cell. iNIS 2016: 89-92 - [c4]Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik:
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. iNIS 2016: 268-273 - [c3]Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik:
FinFET-Based Low Power Address Decoder under Process Variation. iNIS 2016: 274-277 - 2015
- [j2]Vikas Mahor, Manisha Pattanaik:
Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. J. Circuits Syst. Comput. 24(5): 1550073:1-1550073:20 (2015) - [j1]Vikas Mahor, Manisha Pattanaik:
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. J. Low Power Electron. 11(2): 225-235 (2015) - 2012
- [c2]Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik:
A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. ISED 2012: 151-153 - 2011
- [c1]Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor:
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. ISED 2011: 118-123
Coauthor Index
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