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S. H. Amer

Sherif H. Amer

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2010 – 2019

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2016
[c7]
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Ahmed S. Emara, Ahmed H. Madian, Hassanein H. Amer, S. H. Amer, Mohamed B. Abdelhalim:
Testing of memristor ratioed logic (MRL) XOR gate. ICM 2016: 181-184
[c6]
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Manar N. Shaker, Ahmed H. Madian, Mohamed B. Abdelhalim, Sherif H. Amer, Ahmed S. Emara, Hassanein H. Amer:
Effect of open faults in FPGA switch matrices on fault detection mechanisms. ICM 2016: 233-236
[c5]
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Abdullah Abdulslam, S. H. Amer, Ahmed S. Emara, Yehea Ismail:
Evaluation of multi-level buck converters for low-power applications. ISCAS 2016: 794-797
2015
[c4]
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S. H. Amer, Ahmed H. Madian, Ahmed S. Emara:
Memristor-based Center-Of-Gravity (COG) defuzzifier circuit. ECCTD 2015: 1-4
[c3]
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S. H. Amer, Ahmed H. Madian, Ahmed S. Emara:
Design and analysis of memristor-based min-max circuit. ICECS 2015: 187-190
[c2]
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Ahmed S. Emara, Ahmed H. Madian, Hassanein H. Amer, S. H. Amer:
High coverage test for the second generation current conveyor. ICECS 2015: 429-432
2014
[c1]
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S. H. Amer, Ahmed S. Emara, R. Mohie El-Din, M. M. Fouad, Ahmed H. Madian, Hassanein H. Amer, Mohamed B. Abdelhalim, H. H. Draz:
Testing current mode two-input logic gates. CCECE 2014: 1-6

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