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2020 – today
- 2024
[c12]Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin:
Design Automation for Charge Recovery Logic. ISCAS 2024: 1-5- 2021
- [c11]Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin:
Scalable Resonant Power Clock Generation for Adiabatic Logic Design. ISVLSI 2021: 338-342 - 2020
- [c10]Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin:
Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j2]Leo Filippini
, Baris Taskin:
The Adiabatically Driven StrongARM Comparator. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1957-1961 (2019) - [c9]Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin:
Low Swing - Low Frequency Rotary Traveling Wave Oscillators. ISCAS 2019: 1-5 - 2018
- [c8]Leo Filippini, Baris Taskin:
A 900 MHz Charge Recovery Comparator With 40 fJ per Conversion. ISCAS 2018: 1-5 - 2017
- [c7]Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin:
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI. ISCAS 2017: 1-4 - [c6]Leo Filippini, Diane Lim, Lunal Khuon, Baris Taskin:
Wireless charge recovery system for implanted electroencephalography applications in mice. ISQED 2017: 342-345 - [c5]Leo Filippini, Lunal Khuon, Baris Taskin:
Charge recovery implementation of an analog comparator: Initial results. MWSCAS 2017: 1505-1508 - [c4]Leo Filippini, Baris Taskin:
A charge recovery logic system bus. SLIP 2017: 1-4 - 2016
- [c3]Leo Filippini, Baris Taskin:
Charge recovery logic for thermal harvesting applications. ISCAS 2016: 542-545 - 2015
- [j1]Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin:
FinFET-Based Low-Swing Clocking. ACM J. Emerg. Technol. Comput. Syst. 12(2): 13:1-13:20 (2015) - [c2]Leo Filippini, Emre Salman, Baris Taskin:
A wirelessly powered system with charge recovery logic. ICCD 2015: 505-510 - 2014
- [c1]Can Sitik, Leo Filippini, Emre Salman, Baris Taskin:
High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design. ISVLSI 2014: 498-503
Coauthor Index
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