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ORCID19th SLIP 2017: Austin, TX, USA
- ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, SLIP 2017, Austin, TX, USA, June 17, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-1536-2
- Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young:
Fence-aware detailed-routability driven placement. 1-7 - Sai Vineel Reddy Chittamuru
, Ishan G. Thakkar, Sudeep Pasricha:
Analyzing voltage bias and temperature induced aging effects in photonic interconnects for manycore computing. 1-8 - Jinglei Huang, Xiaodong Xu, Lan Yao, Song Chen:
Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs. 1-8 - Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young:
Timing driven routing tree construction. 1-8 - Leo Filippini, Baris Taskin:
A charge recovery logic system bus. 1-4 - Scott Lerner, Eric Leggett, Baris Taskin:
Slew-down: analysis of slew relaxation for low-impact clock buffers. 1-4 - Isuru Daulagala, Ioannis Savidis:
Clock tree synthesis for heterogeneous 3-D integrated circuits. 1-6 - Ulf Schlichtmann:
Frontiers of timing. 1-4
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